公开(公告)号：US10262902B2

公开(公告)日：2019-04-16

申请号：US15761628

申请日：2016-09-21

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Toshihiro Sekigawa ,  Masakazu Hioki ,  Hanpei Koike

IPC: H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H03K17/00 ,  H03K17/693 ,  H03K19/094 ,  H03K19/0944

Abstract: The multiplexer includes a plurality of transmission gates each formed by four-terminal double insulated gate N-type and P-type field effect transistors connected in parallel. One of gates of the N-type gate field effect transistor is connected to a first threshold voltage control node, and a first resistor is connected between the first threshold voltage control node and a first threshold voltage control voltage source. One of gates of the P-type gate field effect transistor is connected to a second threshold voltage control node, and a second resistor is connected between the second threshold voltage control node and a second threshold voltage control voltage source.

公开(公告)号：US20180350690A1

公开(公告)日：2018-12-06

申请号：US15761628

申请日：2016-09-21

Applicant: National Institute of Advanced Industrial Science and Technology

Inventor： Toshihiro Sekigawa ,  Masakazu Hioki ,  Hanpei Koike

IPC: H01L21/8238 ,  H01L27/092 ,  H03K17/693 ,  H03K19/0944

CPC classification number: H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H03K17/00 ,  H03K17/693 ,  H03K19/094 ,  H03K19/0944

Abstract: A multiplexer using an FTMOST and capable of achieving both increase in transfer rate and reduction in leakage current and an integrated circuit using the multiplexer are provided. The multiplexer includes a plurality of pass transistors each formed by a four-terminal double insulated gate field effect transistor. A second gate of the field effect transistor is connected to a threshold voltage control node, and a resistor is connected between the threshold voltage control node and a threshold voltage control voltage source. Also, the multiplexer includes a plurality of transmission gates each formed by four-terminal double insulated gate N-type and P-type field effect transistors connected in parallel. One of gates of the N-type gate field effect transistor is connected to a first threshold voltage control node, and a first resistor is connected between the first threshold voltage control node and a first threshold voltage control voltage source. One of gates of the P-type gate field effect transistor is connected to a second threshold voltage control node, and a second resistor is connected between the second threshold voltage control node and a second threshold voltage control voltage source.