Abstract:
Techniques and systems for synchronizing a clock via a backplane. An apparatus includes a backplane, a clock coupled to or included in the backplane, a synchronization interface, and at least one processing element coupled to the clock via the backplane and coupled to or including the synchronization interface. The at least one processing element may be configured to compare first time information received from the clock via the backplane with second time information received from the synchronization interface. The second time information may be associated with an external clock. The at least one processing element may determine adjustment information based on the comparison and synchronize the clock with an external clock using the adjustment information, via the backplane. The apparatus may be a PXIe chassis. The clock output may be sent to modules plugged into the backplane in order to synchronize them with an external chassis clock, for example.
Abstract:
Techniques and systems for synchronizing a clock via a backplane. An apparatus includes a backplane, a clock coupled to or included in the backplane, a synchronization interface, and at least one processing element coupled to the clock via the backplane and coupled to or including the synchronization interface. The at least one processing element may be configured to compare first time information received from the clock via the backplane with second time information received from the synchronization interface. The second time information may be associated with an external clock. The at least one processing element may determine adjustment information based on the comparison and synchronize the clock with an external clock using the adjustment information, via the backplane. The apparatus may be a PXIe chassis. The clock output may be sent to modules plugged into the backplane in order to synchronize them with an external chassis clock, for example.
Abstract:
Systems and methods for synchronizing clocks across networks using a time-sensitive (TS) network interface controller (NIC). The TS NIC may include a functional unit, a port, a clock, a plurality of input/output queue pairs, and a time stamp unit (TSU). The functional unit may be configured to generate synchronization packets usable by an NTS network timekeeper of a respective NTS network to synchronize the NTS network to the master clock, including using the TSU to generate time stamps for the synchronization packets in accordance with the clock synchronized to the master clock and communicate with the respective NTS network via the port using the corresponding input/output queue pair, including sending the synchronization packets to the NTS network timekeeper of the respective NTS network.
Abstract:
System and methods for synchronizing real time networks. Systems may include a first device located on a first real time network that may include a functional unit, a port, and a plurality of output queues configured for segregation of network packets based on a mapping of one or more additional real time networks to respective output queues. For each of the one or more additional real time networks, synchronization packets may be generated based on a master clock. The packets may be usable by a network timekeeper of the additional real time network to synchronize the additional real time network to the master clock. The synchronization packets may be stored in a respective output queue based on the mapping and may be sent to the network timekeeper of the additional real time network via the port.
Abstract:
System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events.