-
公开(公告)号：US12009054B2
公开(公告)日：2024-06-11
申请号：US17883630
申请日：2022-08-09
发明人： Ying-Tuan Hsu , Tsung-Te Liu , Tzi-Dar Chiueh
摘要： A computing-in-memory circuitry includes multiple digital-to-analog converters, multiple computing arrays, and multiple charge processing networks. The digital-to-analog converters convert external data into input data and the digital-to-analog converters are connected in series with a corresponding plurality of output capacitor pairs. The computing arrays receive the input data from both ends and execute a computation to output a first computing value. The charge processing networks receive and accumulate the first computing values over a predetermined time interval through switching pairs in series with the output capacitor pairs. The charge processing networks evenly distribute charges of the first computing value to selected output capacitor pairs and compare voltage differences between two ends of the output capacitor pairs to output a second computing value.
-
公开(公告)号：US20240330401A1
公开(公告)日：2024-10-03
申请号：US18193659
申请日：2023-03-31
发明人： Po-Jen Chen , Tsung-Hsien Yang , Ting Wang , Tsung-Te Liu
IPC分类号： G06F17/16
CPC分类号： G06F17/16
摘要： A Gaussian elimination computing system and a Gaussian elimination computing method are provided. The Gaussian elimination computing system includes a control circuit, a systolic array, and a memory. The control circuit receives an operation matrix. The systolic array includes a square array formed by a plurality of operating cells. The systolic array is configured to perform a matrix decomposition operation to the operation matrix, to decompose the operation matrix into a lower triangular matrix and an upper triangular matrix. The memory is configured with an operation data block with the same size as the operation matrix for storing the lower triangular matrix and the upper triangular matrix after decomposition.
-
公开(公告)号：US20230402921A1
公开(公告)日：2023-12-14
申请号：US17838289
申请日：2022-06-13
发明人： Bing-Chen Wu , Tsung-Te Liu
CPC分类号： H02M3/158 , H02M3/07 , H02M1/0012
摘要： An adjustable voltage regulator circuit, including a voltage conversion circuit, a voltage conversion controller, and a clock generator, is provided. The voltage conversion circuit receives an input voltage to generate an output voltage. The voltage conversion controller detects the output voltage, compares the output voltage with a reference voltage value, and outputs an enable signal based on a comparison result to control the voltage conversion circuit to adjust the output voltage. The clock generator generates a first clock signal and a second clock signal to respectively drive the voltage conversion circuit and the voltage conversion controller. The voltage conversion controller adjusts the enable signal to gradually adjust the output voltage to a predetermined voltage range.
-
公开(公告)号：US20240055033A1
公开(公告)日：2024-02-15
申请号：US17883630
申请日：2022-08-09
发明人： Ying-Tuan Hsu , Tsung-Te Liu , Tzi-Dar Chiueh
摘要： A computing-in-memory circuitry includes multiple digital-to-analog converters, multiple computing arrays, and multiple charge processing networks. The digital-to-analog converters convert external data into input data and the digital-to-analog converters are connected in series with a corresponding plurality of output capacitor pairs. The computing arrays receive the input data from both ends and execute a computation to output a first computing value. The charge processing networks receive and accumulate the first computing values over a predetermined time interval through switching pairs in series with the output capacitor pairs. The charge processing networks evenly distribute charges of the first computing value to selected output capacitor pairs and compare voltage differences between two ends of the output capacitor pairs to output a second computing value.
-
公开(公告)号：US11329558B2
公开(公告)日：2022-05-10
申请号：US16984577
申请日：2020-08-04
发明人： Fu-Yan Xie , Bing-Chen Wu , Tsung-Te Liu
摘要： A switched-capacitor DC-DC voltage converter and a control method thereof. The switched-capacitor DC-DC voltage converter comprises at least one switch array, comprising a capacitor and at least one switch group, wherein the switch group comprises a plurality of power switches connected to one another in parallel, and one end of the capacitor is electrically connected to the switch group; and a control circuit, converting an input control signal into a control signal set, and outputting the control signal set to the switch group, and the control signal set comprises a plurality of control signals with phase delayed sequentially and the duty cycle reduced sequentially.
-
公开(公告)号：US12113439B2
公开(公告)日：2024-10-08
申请号：US17838289
申请日：2022-06-13
发明人： Bing-Chen Wu , Tsung-Te Liu
CPC分类号： H02M3/07 , G05F1/465 , H02M1/0012
摘要： An adjustable voltage regulator circuit, including a voltage conversion circuit, a voltage conversion controller, and a clock generator, is provided. The voltage conversion circuit receives an input voltage to generate an output voltage. The voltage conversion controller detects the output voltage, compares the output voltage with a reference voltage value, and outputs an enable signal based on a comparison result to control the voltage conversion circuit to adjust the output voltage. The clock generator generates a first clock signal and a second clock signal to respectively drive the voltage conversion circuit and the voltage conversion controller. The voltage conversion controller adjusts the enable signal to gradually adjust the output voltage to a predetermined voltage range.
-
公开(公告)号：US20220014098A1
公开(公告)日：2022-01-13
申请号：US16984577
申请日：2020-08-04
发明人： Fu-Yan Xie , Bing-Chen Wu , Tsung-Te Liu
摘要： A switched-capacitor DC-DC voltage converter and a control method thereof. The switched-capacitor DC-DC voltage converter comprises at least one switch array, comprising a capacitor and at least one switch group, wherein the switch group comprises a plurality of power switches connected to one another in parallel, and one end of the capacitor is electrically connected to the switch group; and a control circuit, converting an input control signal into a control signal set, and outputting the control signal set to the switch group, and the control signal set comprises a plurality of control signals with phase delayed sequentially and the duty cycle reduced sequentially.
-
8.发明授权公开(公告)号：US09941008B1
公开(公告)日：2018-04-10
申请号：US15466878
申请日：2017-03-23
发明人： An-Yeu Wu , Ting-Sheng Chen , Ding-Yuan Lee , Tsung-Te Liu
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： The present disclosure illustrates a ternary content addressable memory (TCAM) device for software defined networking and method thereof. In the TCAM device, M bits of each forwarding rule is stored as a first part into a NAND-Type TCAM, and N bits of the same forwarding rule is stored as a second part into a NOR-Type TCAM. M bits of searching data is compared with the first part to generate a first matching result, N bits of the searching data is compared with the second part to generate a second matching result when the first matching result indicates match, and comparing process for the second part is disabled when the first matching result indicates mismatch. The mechanism is help to improve flexibility of the TCAM in words length and to reduce power consumption.
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.015 秒)
