公开(公告)号：US20240136432A1

公开(公告)日：2024-04-25

申请号：US18096916

申请日：2023-01-13

申请人： National Yang Ming Chiao Tung University ,  National Chung-Shan Institute of Science and Technology

发明人： Edward Yi CHANG ,  You-Chen WENG ,  Min-Lu KAO

IPC分类号： H01L29/778 ,  H01L29/15 ,  H01L29/20

CPC分类号： H01L29/7786 ,  H01L29/15 ,  H01L29/2003

摘要： A high electron mobility transistor includes a growth substrate, a lattice matching layer, an back-barrier layer, an electron blocking layer, a channel layer, an active layer, a source, a gate, and a drain. The lattice matching layer and the back-barrier layer are formed on the growth substrate. The back-barrier layer includes GaN doped with C. The electron blocking layer is formed on the back-barrier layer. The electron blocking layer includes AlGaN, wherein the doping percent of Al atoms of the AlGaN is 3˜5% and the doping percent of Ga atoms of the AlGaN is 95˜97%. The electron blocking layer has a thickness of 2˜5 nm. The channel layer and the active layer are formed on the electron blocking layer. The source, the gate, and the drain are formed on the active layer.

公开(公告)号：US20240234561A9

公开(公告)日：2024-07-11

申请号：US18096916

申请日：2023-01-13

申请人： National Yang Ming Chiao Tung University ,  National Chung-Shan Institute of Science and Technology

发明人： Edward Yi CHANG ,  You-Chen WENG ,  Min-Lu KAO

IPC分类号： H01L29/778 ,  H01L29/15 ,  H01L29/20

CPC分类号： H01L29/7786 ,  H01L29/15 ,  H01L29/2003

摘要： A high electron mobility transistor includes a growth substrate, a lattice matching layer, an back-barrier layer, an electron blocking layer, a channel layer, an active layer, a source, a gate, and a drain. The lattice matching layer and the back-barrier layer are formed on the growth substrate. The back-barrier layer includes GaN doped with C. The electron blocking layer is formed on the back-barrier layer. The electron blocking layer includes AlGaN, wherein the doping percent of Al atoms of the AlGaN is 3˜5% and the doping percent of Ga atoms of the AlGaN is 95˜97%. The electron blocking layer has a thickness of 2˜5 nm. The channel layer and the active layer are formed on the electron blocking layer. The source, the gate, and the drain are formed on the active layer.

公开(公告)号：US20240145575A1

公开(公告)日：2024-05-02

申请号：US18311249

申请日：2023-05-03

申请人： National Yang Ming Chiao Tung University

发明人： Edward Yi CHANG ,  You-Chen WENG ,  Min-Lu KAO

IPC分类号： H01L29/66 ,  H01L29/417 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L29/41725 ,  H01L29/7786

摘要： A semiconductor device includes a substrate, a channel layer, a first barrier layer, a source/drain contact, and a gate layer. The channel layer is on the substrate. The first barrier layer is on the channel layer and the thickness of the first barrier layer is less than 6 nm. The source/drain contact is on the first barrier layer and is directly contact with the first barrier layer. The gate layer is over the first barrier layer.