公开(公告)号：US08121363B2

公开(公告)日：2012-02-21

申请号：US12137837

申请日：2008-06-12

申请人： Ndubuisi Chiakpo ,  Karl J. Duvalsaint ,  Moon J. Kim

发明人： Ndubuisi Chiakpo ,  Karl J. Duvalsaint ,  Moon J. Kim

IPC分类号： G06K9/54

CPC分类号： G06T1/20

摘要： The system permits sharing both thermographic image processing and visualization across a single universal platform, thus allowing for sharing of processor resources and visualization of thermographic images on a variety of imaging (client) devices without high-performance graphical display cards. In a typical embodiment, a (e.g., medical) thermographic image 2D linear registration algorithm is implemented on a Cell Broadband Engine processor, which has nine processor cores on a chip and has a 4-way SIMD unit for each core. This multi-core processor technological advancement allows for the development of a thermographic image processing system that is used for thermographic image capturing modalities. A platform is used to provide a generalized medical thermographic image capturing and processing system, which handles different types of medical thermographic image apparatuses on a single data processing platform.

摘要翻译： 该系统允许在单个通用平台上共享热成像图像处理和可视化，从而允许在不具有高性能图形显示卡的各种成像（客户端）设备上共享处理器资源和热成像图像的可视化。 在典型的实施例中，在Cell宽带引擎处理器上实现（例如，医学）热成像2D线性注册算法，该处理器在芯片上具有九个处理器核心，并且具有用于每个核心的4路SIMD单元。 这种多核处理器技术进步允许开发用于热成像图像捕获模式的热成像图像处理系统。 平台用于提供广泛的医疗热成像图像捕获和处理系统，其在单个数据处理平台上处理不同类型的医用热成像图像设备。

公开(公告)号：US20090310815A1

公开(公告)日：2009-12-17

申请号：US12137837

申请日：2008-06-12

申请人： Ndubuisi Chiakpo ,  Karl J. Duvalsaint ,  Moon Ju Kim

发明人： Ndubuisi Chiakpo ,  Karl J. Duvalsaint ,  Moon Ju Kim

IPC分类号： G06K9/00

CPC分类号： G06T1/20

摘要： The system permits sharing both thermographic image processing and visualization across a single universal platform, thus allowing for sharing of processor resources and visualization of thermographic images on a variety of imaging (client) devices without high-performance graphical display cards. In a typical embodiment, a (e.g., medical) thermographic image 2D linear registration algorithm is implemented on a Cell Broadband Engine processor, which has nine processor cores on a chip and has a 4-way SIMD unit for each core. This multi-core processor technological advancement allows for the development of a thermographic image processing system that is used for thermographic image capturing modalities. A platform is used to provide a generalized medical thermographic image capturing and processing system, which handles different types of medical thermographic image apparatuses on a single data processing platform.

摘要翻译： 该系统允许在单个通用平台上共享热成像图像处理和可视化，从而允许在不具有高性能图形显示卡的各种成像（客户端）设备上共享处理器资源和热成像图像的可视化。 在典型的实施例中，在Cell宽带引擎处理器上实现（例如，医学）热成像2D线性注册算法，该处理器在芯片上具有九个处理器核心，并且具有用于每个核心的4路SIMD单元。 这种多核处理器技术进步允许开发用于热成像图像捕获模式的热成像图像处理系统。 平台用于提供广泛的医疗热成像图像捕获和处理系统，其在单个数据处理平台上处理不同类型的医用热成像图像设备。

公开(公告)号：US09886389B2

公开(公告)日：2018-02-06

申请号：US12276072

申请日：2008-11-21

申请人： Dan P. Dumarot ,  Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim ,  Eugene B. Risi

发明人： Dan P. Dumarot ,  Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim ,  Eugene B. Risi

IPC分类号： G06F12/08 ,  G06F12/0888 ,  G06F11/16 ,  G06F12/0811 ,  G06F11/20 ,  G06F12/0813 ,  G06F12/084

CPC分类号： G06F12/0888 ,  G06F11/1666 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1032

摘要： This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

公开(公告)号：US08806129B2

公开(公告)日：2014-08-12

申请号：US12275508

申请日：2008-11-21

申请人： Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim

发明人： Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim

IPC分类号： G06F12/08

CPC分类号： G06F12/084 ,  G06F12/0811

摘要： Specifically, under the present invention an available on-chip memory is coupled to another logic core or memory (e.g., cache) unit using a set of cache managers. Specifically, each cache manager is coupled to the input and output of a cache memory unit. This allows the assigned memory to become an extension of the same level cache, next level cache memory, or memory buffer. This also allows the recovery of a memory block whose logic core is not operational, and is used to improve cache memory performance of the system. It should be understood in advance the teachings herein are typically applied to a Multi-Core Processor (MCP), although this need not be the case.

摘要翻译： 具体地说，在本发明中，使用一组缓存管理器将可用的片上存储器耦合到另一个逻辑核心或存储器（例如，高速缓存）单元。 具体地，每个高速缓存管理器耦合到高速缓冲存储器单元的输入和输出。 这允许分配的内存成为同一级缓存，下一级高速缓存或内存缓冲区的扩展。 这也允许恢复其逻辑内核不可操作的内存块，并用于提高系统的高速缓存内存性能。 应该预先理解这里的教导通常应用于多核处理器（MCP），尽管不一定是这种情况。

公开(公告)号：US20100082941A1

公开(公告)日：2010-04-01

申请号：US12241332

申请日：2008-09-30

申请人： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

发明人： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

IPC分类号： G06F15/76 ,  G06F9/06

CPC分类号： G06F9/5027 ,  G06F2209/509 ,  Y02D10/22

摘要： The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

摘要翻译： 本公开应用于具有一组（例如，一个或多个）控制元件（例如，MPE）和一组子处理元件（例如，SPE）的通用微处理器架构。 在这种安排下，MPEs和SPE的组织方式是使用较少数量的MPE使用体现为一组虚拟控制线程的程序代码控制一组SPE的行为。 该安排还使MPEs能够将功能委托给一个或多个SPE组，使得这些SPE组将充当伪MPE。 伪MPE将利用伪虚拟化控制线程来控制其他组的SPE的行为。 在典型的实施例中，该装置包括耦合到与核耦合的电源的MCP以向每个核（或核心组）提供电源电压以及控制数字元件和子处理元件的多个实例。

公开(公告)号：US08438404B2

公开(公告)日：2013-05-07

申请号：US12241332

申请日：2008-09-30

申请人： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

发明人： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

IPC分类号： G06F13/00 ,  G06F7/04 ,  G06F15/173 ,  G06F9/45 ,  G06F15/00 ,  G06F9/46 ,  H04L12/28

CPC分类号： G06F9/5027 ,  G06F2209/509 ,  Y02D10/22

摘要： The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

摘要翻译： 本公开应用于具有一组（例如，一个或多个）控制元件（例如，MPE）和一组子处理元件（例如，SPE）的通用微处理器架构。 在这种安排下，MPEs和SPE的组织方式是使用较少数量的MPE使用体现为一组虚拟控制线程的程序代码控制一组SPE的行为。 该安排还使MPEs能够将功能委托给一个或多个SPE组，使得这些SPE组将充当伪MPE。 伪MPE将利用伪虚拟化控制线程来控制其他组的SPE的行为。 在典型的实施例中，该装置包括耦合到与核耦合的电源的MCP以向每个核（或核心组）提供电源电压以及控制数字元件和子处理元件的多个实例。

公开(公告)号：US20100131717A1

公开(公告)日：2010-05-27

申请号：US12276072

申请日：2008-11-21

申请人： Dan P. Dumarot ,  Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim ,  Eugene B. Risi

发明人： Dan P. Dumarot ,  Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim ,  Eugene B. Risi

IPC分类号： G06F12/08

CPC分类号： G06F12/0888 ,  G06F11/1666 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F2212/1032

摘要： This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

摘要翻译： 本发明描述了一种用于多核处理器的装置，计算机体系结构，存储器结构，存储器控制和高速缓存存储器操作方法。 逻辑内核以低产出或致命性能绕过即时缓存单元。 核心安装（多个）高速缓存单元可能已被其他逻辑内核使用。 所选高速缓存存储单元提供具有相同内容的多个逻辑核。 共享高速缓冲存储器单元为所有安装核心提供缓存搜索，命中，未命中和回写功能。 该方法通过共享可能已经接合其他逻辑核心的高速缓存存储器块来恢复其高速缓冲存储器块不可操作的逻辑核心。 该方法用于提高剩余系统的可靠性和性能。

公开(公告)号：US20100131716A1

公开(公告)日：2010-05-27

申请号：US12275552

申请日：2008-11-21

申请人： Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim

发明人： Karl J. Duvalsaint ,  Daeik Kim ,  Moon J. Kim

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0811 ,  G06F11/1666 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0888 ,  G06F2212/1032

摘要： This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core shares requests when faced with immediate cache memory units having low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

摘要翻译： 本发明描述了一种用于多核处理器的装置，计算机体系结构，存储器结构，存储器控制和高速缓存存储器操作方法。 当面对具有低产量或致命性能的即时高速缓冲存储器单元时，逻辑核心共享请求。 核心安装（多个）高速缓存单元可能已被其他逻辑内核使用。 所选高速缓存存储单元提供具有相同内容的多个逻辑核。 共享高速缓冲存储器单元为所有安装核心提供缓存搜索，命中，未命中和回写功能。 该方法通过共享可能已经接合其他逻辑核心的高速缓存存储器块来恢复其高速缓冲存储器块不可操作的逻辑核心。 该方法用于提高剩余系统的可靠性和性能。

公开(公告)号：US08341638B2

公开(公告)日：2012-12-25

申请号：US12241697

申请日：2008-09-30

申请人： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

发明人： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

IPC分类号： G06F9/46 ,  G06F9/44 ,  G06F13/00 ,  G06F7/38 ,  H04L12/56

CPC分类号： G06F9/4893 ,  G06F2209/483 ,  Y02D10/24

摘要： This disclosure describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization across physical boundaries that define physical partitions in a symmetric MCP. Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). The arrangement also enables MPEs to delegate functionality to one or more groups of SPEs such that those group(s) of SPEs may act as pseudo MPEs. Such delegation may occur across the physical boundaries. Regardless, the pseudo MPEs may utilize pseudo virtualized control threads to control the behavior of other groups of SPEs also across physical boundaries.

摘要翻译： 本公开描述了用于MPE的装置，计算机体系结构，方法，操作系统，编译器和应用程序产品，以及跨物理边界的虚拟化，其定义对称MCP中的物理分区。 除其他之外，本公开应用于具有一组（例如，一个或多个）控制/主处理元件（例如MPE）和一组子处理元件（例如SPE）的通用微处理器架构。 该安排还使MPE能够将功能委派给一个或多个SPE组，使得那些SPE组可以充当伪MPE。 这种授权可能会跨物理边界发生。 无论如何，伪MPE可以利用伪虚拟化控制线程来控制物理边界上的其他SPE组的行为。

公开(公告)号：US20120297164A1

公开(公告)日：2012-11-22

申请号：US13563160

申请日：2012-07-31

申请人： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

发明人： Karl J. Duvalsaint ,  Harm P. Hofstee ,  Daeik Kim ,  Moon J. Kim

IPC分类号： G06F15/76

CPC分类号： G06F9/5077 ,  Y02D10/22 ,  Y02D10/36

摘要： This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

摘要翻译： 本发明描述了用于MPE的设备，计算机体系结构，方法，操作系统，编译器和应用程序产品以及对称MCP中的虚拟化。 本公开应用于具有一组（例如，一个或多个）控制元件（例如，MPE）和一组子处理元件（例如，SPE）的通用微处理器架构。 在这种安排下，MPEs和SPE的组织方式是以较小数量的MPE来控制一组SPE的行为。 该设备使得MPE内的虚拟化控制线程可以分配给不同的SPE组，以便控制它们。 该装置还包括耦合到与核耦合的电源的MCP以向每个核（或核心组）提供电源电压以及控制数字元件和子处理元件的多个实例。