公开(公告)号：US20150277924A1

公开(公告)日：2015-10-01

申请号：US14231028

申请日：2014-03-31

Applicant: Netronome Systems, Inc.

Inventor： Frank J. Zappulla ,  Steven W. Zagorianakos ,  Rajesh Vaidheeswarran

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/3836 ,  G06F9/3877 ,  G06F9/46 ,  G06F9/4881 ,  G06F21/00 ,  G06F21/72

Abstract: A dispatcher circuit receives sets of instructions from an instructing entity. Instructions of the set of a first type are put into a first queue circuit, instructions of the set of a second type are put into a second queue circuit, and so forth. The first queue circuit dispatches instructions of the first type to one or more processing engines and records when the instructions of the set are completed. When all the instructions of the set of the first type have been completed, then the first queue circuit sends the second queue circuit a go signal, which causes the second queue circuit to dispatch instructions of the second type and to record when they have been completed. This process proceeds from queue circuit to queue circuit. When all the instructions of the set have been completed, then the dispatcher circuit returns an “instructions done” to the original instructing entity.

Abstract translation: 调度器电路从指导实体接收指令集。 将第一类型的集合的指令放入第一队列电路中，将第二类型的集合的指令放入第二队列电路中，等等。 第一个队列电路将第一类型的指令分配给一个或多个处理引擎，并且当该组的指令完成时记录。 当所述第一类型的所有指令已经完成时，第一队列电路向第二队列电路发送去信号，这使得第二队列电路调度第二类型的指令并记录它们何时完成 。 该过程从队列电路进行到队列电路。 当集合的所有指令已经完成时，调度器电路向原始指令实体返回“完成指令”。

公开(公告)号：US10031758B2

公开(公告)日：2018-07-24

申请号：US14231028

申请日：2014-03-31

Applicant: Netronome Systems, Inc.

Inventor： Frank J. Zappulla ,  Steven W. Zagorianakos ,  Rajesh Vaidheeswarran

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F21/72

Abstract: A dispatcher circuit receives sets of instructions from an instructing entity. Instructions of the set of a first type are put into a first queue circuit, instructions of the set of a second type are put into a second queue circuit, and so forth. The first queue circuit dispatches instructions of the first type to one or more processing engines and records when the instructions of the set are completed. When all the instructions of the set of the first type have been completed, then the first queue circuit sends the second queue circuit a go signal, which causes the second queue circuit to dispatch instructions of the second type and to record when they have been completed. This process proceeds from queue circuit to queue circuit. When all the instructions of the set have been completed, then the dispatcher circuit returns an “instructions done” to the original instructing entity.