公开(公告)号：US20080272432A1

公开(公告)日：2008-11-06

申请号：US11687813

申请日：2007-03-19

Applicant: Niraj SUBBA ,  Ciby THURUTHIYIL

Inventor： Niraj SUBBA ,  Ciby THURUTHIYIL

IPC: H01L29/786

CPC classification number: H01L29/66628 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78639

Abstract: Accumulation mode MOS transistors and methods for fabricating such transistors are provided. A method comprises providing an SOI layer disposed overlying a substrate with an insulating layer interposed therebetween. The SOI layer is impurity doped with a first dopant of a first conductivity type and spacers and a gate stack having a sacrificial polycrystalline silicon gate electrode is formed on the SOI layer. A first and a second silicon region are impurity doped with a second dopant of the first conductivity type. The first silicon region and the second silicon region are aligned to the gate stack and spacers. The sacrificial polycrystalline silicon gate electrode is removed and a metal-comprising gate electrode is formed from a metal-comprising material having a mid-gap work function.

Abstract translation: 提供了累积模式MOS晶体管及其制造方法。 一种方法包括提供设置在衬底上的SOI层，其间插入有绝缘层。 SOI层是掺杂有第一导电类型的第一掺杂剂的杂质，并且在SOI层上形成具有牺牲多晶硅栅电极的间隔物和栅叠层。 第一和第二硅区是掺杂有第一导电类型的第二掺杂剂的杂质。 第一硅区域和第二硅区域与栅叠层和间隔物对准。 去除牺牲多晶硅栅电极，并且由具有中缝功函数的含金属的材料形成含金属的栅电极。