公开(公告)号：US20080272432A1

公开(公告)日：2008-11-06

申请号：US11687813

申请日：2007-03-19

申请人： Niraj SUBBA ,  Ciby THURUTHIYIL

发明人： Niraj SUBBA ,  Ciby THURUTHIYIL

IPC分类号： H01L29/786

CPC分类号： H01L29/66628 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78639

摘要： Accumulation mode MOS transistors and methods for fabricating such transistors are provided. A method comprises providing an SOI layer disposed overlying a substrate with an insulating layer interposed therebetween. The SOI layer is impurity doped with a first dopant of a first conductivity type and spacers and a gate stack having a sacrificial polycrystalline silicon gate electrode is formed on the SOI layer. A first and a second silicon region are impurity doped with a second dopant of the first conductivity type. The first silicon region and the second silicon region are aligned to the gate stack and spacers. The sacrificial polycrystalline silicon gate electrode is removed and a metal-comprising gate electrode is formed from a metal-comprising material having a mid-gap work function.

摘要翻译： 提供了累积模式MOS晶体管及其制造方法。 一种方法包括提供设置在衬底上的SOI层，其间插入有绝缘层。 SOI层是掺杂有第一导电类型的第一掺杂剂的杂质，并且在SOI层上形成具有牺牲多晶硅栅电极的间隔物和栅叠层。 第一和第二硅区是掺杂有第一导电类型的第二掺杂剂的杂质。 第一硅区域和第二硅区域与栅叠层和间隔物对准。 去除牺牲多晶硅栅电极，并且由具有中缝功函数的含金属的材料形成含金属的栅电极。

公开(公告)号：US20140129999A1

公开(公告)日：2014-05-08

申请号：US13671226

申请日：2012-11-07

申请人： Kaveri MATHUR ,  Sriraaman SRIDHARAN ,  Ciby THURUTHIYIL

发明人： Kaveri MATHUR ,  Sriraaman SRIDHARAN ,  Ciby THURUTHIYIL

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5036 ,  G06F17/5045

摘要： An approach for methodology enabling a verification of IC designs that compensates for degraded performance due to a physical placement, particularly a stacked physical placement is disclosed. A set of stacked devices from a plurality of devices in an IC design is determined. One or more instance parameters indicating a physical placement of a device in the set is determined. A compensation metric indicating one or more electrical characteristics of a device in the set is determined based on the one or more instance parameters.

摘要翻译： 公开了一种能够验证IC设计的方法，该IC设计补偿由于物理放置，特别是堆叠的物理放置而导致的性能下降。 确定来自IC设计中的多个设备的一组堆叠设备。 确定指示设备在设备中的物理放置的一个或多个实例参数。 基于一个或多个实例参数来确定指示该组中的设备的一个或多个电特性的补偿度量。

公开(公告)号：US20100207175A1

公开(公告)日：2010-08-19

申请号：US12371846

申请日：2009-02-16

申请人： Sushant SURYAGANDH ,  Ciby THURUTHIYIL ,  Kaveri MATHUR

发明人： Sushant SURYAGANDH ,  Ciby THURUTHIYIL ,  Kaveri MATHUR

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/78654

摘要： A semiconductor transistor device is provided. The transistor device includes a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, a source region in the layer of semiconductor material, and a drain region in the layer of semiconductor material. The source region has a stress-inducing semiconductor material located therein, while the drain region is free of any stress-inducing semiconductor material. This asymmetric arrangement of stress-inducing elements results in relatively high source-body leakage, and relatively low drain-body leakage, which is beneficial in analog circuit applications.

摘要翻译： 提供一种半导体晶体管器件。 晶体管器件包括半导体材料层，覆盖半导体材料层的栅极结构，半导体材料层中的源极区域和半导体材料层中的漏极区域。 源极区域具有位于其中的应力诱导半导体材料，而漏极区域没有任何应力诱导半导体材料。 应力诱导元件的这种不对称布置导致相对较高的源体泄漏以及相对低的漏极体泄漏，这在模拟电路应用中是有益的。