公开(公告)号：US4272827A

公开(公告)日：1981-06-09

申请号：US21011

申请日：1979-03-16

申请人： Norio Inui ,  Noriaki Kume ,  Tetsuro Okamoto

发明人： Norio Inui ,  Noriaki Kume ,  Tetsuro Okamoto

IPC分类号： G06F7/52 ,  G06F7/527 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/5355

摘要： A division processing system performs 2N-bit precision division processing by effectively using division processing circuitry with N-bit precision. The system performs the division with 2N-bit precision as follows: ##EQU1## (n=N: the number of digit positions in selected binary numbers A, B, C and D). The above expression is approximated to the form of Q.sub.1 +Q.sub.2 .times.2-n (Q.sub.1, Q.sub.2 : binary numbers). The binary numbers Q.sub.1 and Q.sub.2 are respectively operated on by the division processing circuitry with N-bit precision. By effective control, the error caused during the division processing of Q.sub.1 is used as a part of the data for performing the division processing of Q.sub.2, thus effectively transferring any error evolving during the processing of Q.sub.1 to Q.sub.2. The function is performed in a system having only four registers, each of N-bit capacity (precision), and an operation register, multiplication circuitry, division circuitry, and a shift circuit, affording proper control of data transfer between the registers.

摘要翻译： 分割处理系统通过有效地使用N位精度的分割处理电路来执行2N位精度分割处理。 系统以2N位精度进行除法，如下所示：（n = N：选定二进制数A，B，C和D中的位数）。 上述表达式近似为Q1 + Q2x2-n（Q1，Q2：二进制数）的形式。 二进制数Q1和Q2分别由具有N位精度的分割处理电路操作。 通过有效控制，在Q1的分割处理期间引起的误差被用作执行Q2的分割处理的数据的一部分，从而有效地将在Q1处理期间发生的任何错误转移到Q2。 该功能在仅具有四个寄存器，N位容量（精度）和操作寄存器，乘法电路，分频电路和移位电路的系统中执行，从而提供对寄存器之间的数据传输的适当控制。