公开(公告)号：US20170229055A1

公开(公告)日：2017-08-10

申请号：US15016294

申请日：2016-02-05

Applicant: Novatek Microelectronics Corp.

Inventor： Jen-Chieh Hu ,  Jung-Chieh Cheng

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3677 ,  G09G5/18 ,  G09G2230/00 ,  G09G2310/0291 ,  G09G2310/063 ,  G09G2310/08 ,  G09G2320/0219 ,  G09G2320/0693 ,  G09G2330/026 ,  G09G2330/12

Abstract: A display apparatus, a gate driver and an operation method thereof are provided. The gate driver includes a first input buffer and a gate line driving circuit. An input terminal of the first input buffer is configured to receive a timing control signal from the outside of the gate driver. The gate line driving circuit is coupled to an output terminal of the first input buffer. The gate line driving circuit is configured to scan a plurality of gate lines of the display panel based on the control of the timing control signal. An output impedance of the first input buffer is correspondingly adjusted according to the coupling noise of the gate driver.

公开(公告)号：US09847053B2

公开(公告)日：2017-12-19

申请号：US15016294

申请日：2016-02-05

Applicant: Novatek Microelectronics Corp.

Inventor： Jen-Chieh Hu ,  Jung-Chieh Cheng

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3677 ,  G09G5/18 ,  G09G2230/00 ,  G09G2310/0291 ,  G09G2310/063 ,  G09G2310/08 ,  G09G2320/0219 ,  G09G2320/0693 ,  G09G2330/026 ,  G09G2330/12

Abstract: A display apparatus, a gate driver and an operation method thereof are provided. The gate driver includes a first input buffer and a gate line driving circuit. An input terminal of the first input buffer is configured to receive a timing control signal from the outside of the gate driver. The gate line driving circuit is coupled to an output terminal of the first input buffer. The gate line driving circuit is configured to scan a plurality of gate lines of the display panel based on the control of the timing control signal. An output impedance of the first input buffer is correspondingly adjusted according to the coupling noise of the gate driver.

公开(公告)号：US10943518B2

公开(公告)日：2021-03-09

申请号：US16527054

申请日：2019-07-31

Applicant: Novatek Microelectronics Corp.

Inventor： Yu-Hung Su ,  Cheng-Yu Tsai ,  Jung-Chieh Cheng

IPC: G09G3/20

Abstract: A timing control circuit and an operating method thereof are provided. The timing control circuit includes a first clock generating circuit, a second clock generating circuit and a control timing generating circuit. The control timing generating circuit is coupled to the first clock generating circuit to receive a first clock signal. The control timing generating circuit is coupled to the second clock generating circuit to receive a second clock signal. The control timing generating circuit starts timing from a first reference time point according to the first clock signal for determining a second reference time point. The control timing generating circuit starts timing from the second reference time point according to the second clock signal for determining a time point of a trailing edge of a current line pulse of a scan reference signal, wherein the current line pulse corresponds to a current scan line of a display panel.

公开(公告)号：US20210035479A1

公开(公告)日：2021-02-04

申请号：US16527054

申请日：2019-07-31

Applicant: Novatek Microelectronics Corp.

Inventor： Yu-Hung Su ,  Cheng-Yu Tsai ,  Jung-Chieh Cheng

IPC: G09G3/20

Abstract: A timing control circuit and an operating method thereof are provided. The timing control circuit includes a first clock generating circuit, a second clock generating circuit and a control timing generating circuit. The control timing generating circuit is coupled to the first clock generating circuit to receive a first clock signal. The control timing generating circuit is coupled to the second clock generating circuit to receive a second clock signal. The control timing generating circuit starts timing from a first reference time point according to the first clock signal for determining a second reference time point. The control timing generating circuit starts timing from the second reference time point according to the second clock signal for determining a time point of a trailing edge of a current line pulse of a scan reference signal, wherein the current line pulse corresponds to a current scan line of a display panel.