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公开(公告)号:US09843715B2
公开(公告)日:2017-12-12
申请号:US14614925
申请日:2015-02-05
Applicant: OLYMPUS CORPORATION
Inventor: Takayuki Suzuki , Manabu Ichikawa , Shinichiro Ishikane , Tsutomu Kuroki , Yasutaka Sawa , Ayako Tsunefuji
CPC classification number: H04N5/23219 , H04N5/2354
Abstract: A display device includes an image pickup device, a stroboscope, and a stroboscopic image prediction creation unit. The stroboscope applies stroboscopic light to a subject together with the photography by the image pickup device. The stroboscopic image prediction creation unit acquires distance distribution information showing the distribution of distance information relative to the subject of the photography of the subject together with the application of stroboscopic light, and predict in advance, on the basis of the distance distribution information, a stroboscopic image for the photography of the subject together with the application of the stroboscopic light.
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公开(公告)号:US20190324646A1
公开(公告)日:2019-10-24
申请号:US16458499
申请日:2019-07-01
Applicant: OLYMPUS CORPORATION
Inventor: Shinsuke Homma , Tomonori Yonemoto , Junichi Shimoyama , Akira Ueno , Tsutomu Kuroki , Tomomi Hirano
Abstract: A memory access device for controlling accesses to a memory having a plurality of banks by a plurality of processing blocks including at least one high-priority processing block, connected to a common data bus, and outputting access requests for requesting access to the memory has a memory controller connected to the data bus to control access to the connected memory in response to the access requests while outputting operation information of the memory; and an access selection unit configured to change a designation sequence of the banks according to the operation information at the time when the high-priority processing block continuously accesses the plurality of banks and output the access requests in the changed sequence, wherein the access selection unit is configured to further change the designation sequence according to the changing operation information during a period while the access requests are not accepted by the memory controller.
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