公开(公告)号：US20150228650A1

公开(公告)日：2015-08-13

申请号：US14175847

申请日：2014-02-07

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tianjia Sun ,  Lingchuan Li ,  Shumin Wu

IPC: H01L27/092 ,  H01L23/528

CPC classification number: H01L27/092 ,  G06F17/5077 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip includes CMOS integrated circuit cells arranged in a semiconductor layer, each including first and second active regions, having first and second polarities, respectively. A first power rail is routed along boundaries of the CMOS integrated circuit cells proximate to the first active regions. A second power rail is routed over second active regions. Global routing channels are routed over the second active regions such that the second power rail is disposed between the global routing channels and the first power rail. The global routing channels are coupled between the CMOS integrated circuit cells to couple the CMOS integrated circuit cells together globally in the integrated circuit chip.

Abstract translation: 集成电路芯片包括布置在半导体层中的分别具有第一和第二极性的第一和第二有源区的CMOS集成电路单元。 第一电源轨沿着靠近第一有源区的CMOS集成电路单元的边界布线。 第二个电力轨道路由在第二个有源区域上。 全局路由信道被路由在第二有源区域上，使得第二电力轨设置在全局路由信道和第一电力轨道之间。 全局路由信道耦合在CMOS集成电路单元之间，以将集成电路芯片中的CMOS集成电路单元集成在一起。

公开(公告)号：US09136267B2

公开(公告)日：2015-09-15

申请号：US14175847

申请日：2014-02-07

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Tianjia Sun ,  Lingchuan Li ,  Shumin Wu

IPC: H01L29/73 ,  H01L27/092 ,  H01L23/528

CPC classification number: H01L27/092 ,  G06F17/5077 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip includes CMOS integrated circuit cells arranged in a semiconductor layer, each including first and second active regions, having first and second polarities, respectively. A first power rail is routed along boundaries of the CMOS integrated circuit cells proximate to the first active regions. A second power rail is routed over second active regions. Global routing channels are routed over the second active regions such that the second power rail is disposed between the global routing channels and the first power rail. The global routing channels are coupled between the CMOS integrated circuit cells to couple the CMOS integrated circuit cells together globally in the integrated circuit chip.

Abstract translation: 集成电路芯片包括布置在半导体层中的分别具有第一和第二极性的第一和第二有源区的CMOS集成电路单元。 第一电源轨沿着靠近第一有源区的CMOS集成电路单元的边界布线。 第二个电力轨道路由在第二个有源区域上。 全局路由信道被路由在第二有源区域上，使得第二电力轨设置在全局路由信道和第一电力轨道之间。 全局路由信道耦合在CMOS集成电路单元之间，以将集成电路芯片中的CMOS集成电路单元集成在一起。