公开(公告)号：US10884962B2

公开(公告)日：2021-01-05

申请号：US16643605

申请日：2018-09-20

Applicant: OMRON Corporation

Inventor： Maki Nishimura ,  Megumu Asano

IPC: G06F13/36 ,  G06F13/362 ,  G06F11/07

Abstract: A main control section (30) of a slave device (3) include a slave controller (31), a processor (32), and a watchdog circuit (33) which are configured as a one-chip integrated circuit. In a case where the watchdog circuit (33) has detected that a malfunction has occurred in an operation of the main control section (30), the watchdog circuit (33) resets the processor (32) while not stopping an operation of the slave controller (31).

公开(公告)号：US09971715B2

公开(公告)日：2018-05-15

申请号：US14950063

申请日：2015-11-24

Applicant: OMRON Corporation

Inventor： Hirohito Mizumoto ,  Yoshimi Niwa ,  Megumu Asano ,  Hajime Ujiie ,  Satoshi Yamawaki

IPC: G06F13/38 ,  G06F13/36 ,  G06F13/42 ,  H04L12/40 ,  H04L12/407

CPC classification number: G06F13/36 ,  G06F13/38 ,  G06F13/4265 ,  H04L12/40169 ,  H04L12/407

Abstract: A slave device is realized that establishes a link with a master device or another slave device such that a large link delay hardly occurs. The slave device includes a PHY unit, a COM unit, and a MPU unit. The PHY unit starts an operation according to the specification of the AutoMDI/MDI-X function when the slave device is turned on or the PHY unit itself is reset. After a predetermined time period has elapsed, the MPU unit resets the COM unit, and the PHY unit is reset in response to the reset of the COM unit.