利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

6 条记录 (耗时 0.017 秒)

    NAVIGATING TRACE DATA
    1.
    发明申请
    NAVIGATING TRACE DATA 有权
    导航跟踪数据

    公开(公告)号：US20060259827A1

    公开(公告)日：2006-11-16

    申请号：US11383474

    申请日：2006-05-15

    申请人： Oliver SOHM ,  Brian CRUICKSHANK ,  Manisha AGARWALA ,  Gary Swoboda

    发明人： Oliver SOHM ,  Brian CRUICKSHANK ,  Manisha AGARWALA ,  Gary Swoboda

    IPC分类号： G06F11/00

    CPC分类号： G06F11/3644 ,  G06F11/3648

    摘要： Navigating trace data. A traced program, or the operating system responsible for the traced program, writes index values to a particular hardware location, which index values become part of the trace data by operation of hardware devices in the target system. A debug-trace program (executed either in an attached host computer or as an embedded debugger) uses the index values to assist the user of the debug-trace program in navigating to particular portions of the trace data based on the index values.

    摘要翻译： 浏览跟踪数据。 跟踪的程序或负责跟踪的程序的操作系统将索引值写入特定的硬件位置，通过目标系统中的硬件设备的操作，哪些索引值成为跟踪数据的一部分。 调试跟踪程序（在附加的主机计算机中或作为嵌入式调试器执行）使用索引值来帮助调试跟踪程序的用户根据索引值导航到跟踪数据的特定部分。

    SYSTEMS AND METHODS FOR SECURE DEBUGGING AND PROFILING OF A COMPUTER SYSTEM
    2.
    发明申请
    SYSTEMS AND METHODS FOR SECURE DEBUGGING AND PROFILING OF A COMPUTER SYSTEM 有权
    用于安全计算机系统的调试和配置的系统和方法

    公开(公告)号：US20060259726A1

    公开(公告)日：2006-11-16

    申请号：US11383467

    申请日：2006-05-15

    申请人： Lewis NARDINI ,  Manisha AGARWALA ,  Oliver SOHM

    发明人： Lewis NARDINI ,  Manisha AGARWALA ,  Oliver SOHM

    IPC分类号： G06F12/00

    CPC分类号： G06F11/3656 ,  G06F12/0897

    摘要： The present disclosure describes methods and systems for secure debugging and profiling of a computer system. Some illustrative embodiments may include a system including a processor with a first processing stage and a first attribute register associated with the first processing stage, and including a memory system coupled to the processor. An instruction and an attribute value are stored within the memory system, wherein the instruction is loaded into the first processing stage and the attribute value is loaded into the first attribute register. Export of debug and profiling data from the first processing stage is disabled if the attribute value in the first attribute register indicates that the instruction in the first processing stage is a secure instruction, and further indicates that secure emulation is disabled.

    摘要翻译： 本公开描述了用于安全调试和分析计算机系统的方法和系统。 一些说明性实施例可以包括包括具有第一处理级的处理器和与第一处理级相关联的第一属性寄存器的系统的系统，并且包括耦合到处理器的存储器系统。 指令和属性值被存储在存储器系统内，其中指令被加载到第一处理级，并且属性值被加载到第一属性寄存器中。 如果第一属性寄存器中的属性值指示第一处理阶段中的指令是安全指令，并且进一步指示安全仿真被禁用，则禁止从第一处理阶段导出调试和分析数据。

    SYNC POINT INDICATING TRACE STREAM STATUS
    4.
    发明申请
    SYNC POINT INDICATING TRACE STREAM STATUS 审中-公开
    同步点指示踪迹状态

    公开(公告)号：US20070288905A1

    公开(公告)日：2007-12-13

    申请号：US11383668

    申请日：2006-05-16

    申请人： Manisha AGARWALA ,  John M. Johnsen

    发明人： Manisha AGARWALA ,  John M. Johnsen

    IPC分类号： G06F9/44

    CPC分类号： G06F11/3476

    摘要： A system comprising a processor adapted to execute software code and a trace logic coupled to the processor and adapted to collect trace information associated with the processor while the software code is executed. The trace information is partitioned into multiple trace streams. The trace logic inserts one or more status bits into a trace stream, the one or more status bits indicative of a current status of one or more of the trace streams and not indicative of a previous status of the one or more of the trace streams.

    摘要翻译： 一种系统，包括适于执行软件代码的处理器和耦合到所述处理器的跟踪逻辑，并适于在执行所述软件代码的同时收集与所述处理器相关联的跟踪信息。 跟踪信息被分割成多个跟踪流。 跟踪逻辑将一个或多个状态位插入到跟踪流中，一个或多个状态位指示一个或多个跟踪流的当前状态，并且不指示一个或多个跟踪流的先前状态。

    EFFICIENT TRACE TRIGGERING
    5.
    发明申请
    EFFICIENT TRACE TRIGGERING 有权
    有效追踪

    公开(公告)号：US20080010550A1

    公开(公告)日：2008-01-10

    申请号：US11420914

    申请日：2006-05-30

    申请人： Manisha AGARWALA

    发明人： Manisha AGARWALA

    IPC分类号： G06F11/00

    CPC分类号： G06F11/3636

    摘要： A system comprising a processor core adapted to execute software code and a trace logic coupled to the processor core and comprising a storage. The storage comprises at least one bit that indicates a condition and status information. The trace logic generates a trace information stream associated with the processor core as the core executes the software code. If the condition is satisfied, the trace logic adjusts a status of the trace stream in accordance with the status information.

    摘要翻译： 一种系统，包括适于执行软件代码的处理器核心和耦合到所述处理器核心并包括存储器的跟踪逻辑。 存储器包括指示条件和状态信息的至少一个位。 当核心执行软件代码时，跟踪逻辑产生与处理器核心相关联的跟踪信息流。 如果满足条件，则跟踪逻辑根据状态信息来调整跟踪流的状态。

    EFFICIENT TRANSFER OF TIMING INFORMATION
    6.
    发明申请
    EFFICIENT TRANSFER OF TIMING INFORMATION 审中-公开
    时间信息的有效转移

    公开(公告)号：US20070288906A1

    公开(公告)日：2007-12-13

    申请号：US11383680

    申请日：2006-05-16

    申请人： Manisha AGARWALA ,  John M. Johnsen

    发明人： Manisha AGARWALA ,  John M. Johnsen

    IPC分类号： G06F9/44

    CPC分类号： G06F11/348

    摘要： A system comprising a processor adapted to execute software code and a trace logic coupled to the processor and adapted to generate a timing packet comprising timing bits. At least some of the timing bits are associated with clock cycles elapsed during execution of the software code. The trace logic flushes invalid timing bits with a common bit, the common bit being an inverse of a valid timing bit.

    摘要翻译： 一种包括处理器的系统，所述处理器适于执行耦合到所述处理器的软件代码和跟踪逻辑，并适于产生包括定时位的定时分组。 至少一些定时位与在执行软件代码期间经过的时钟周期相关联。 跟踪逻辑用公共位刷新无效定时位，公共位是有效定时位的倒数。