公开(公告)号：US09766894B2

公开(公告)日：2017-09-19

申请号：US14539104

申请日：2014-11-12

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： C. John Glossner ,  Gary J. Nacer ,  Murugappan Senthilvelan ,  Vitaly Kalashnikov ,  Arthur J. Hoane ,  Paul D'Arcy ,  Sabin D. Iancu ,  Shenghong Wang

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3822 ,  G06F9/3836 ,  G06F9/3853

Abstract: A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.

公开(公告)号：US20150220342A1

公开(公告)日：2015-08-06

申请号：US14539104

申请日：2014-11-12

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： C. John Glossner ,  Gary J. Nacer ,  Murugappan Senthilvelan ,  Vitaly Kalashnikov ,  Arthur J. Hoane ,  Paul D'Arcy ,  Sabin D. Iancu ,  Shenghong Wang

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3822 ,  G06F9/3836 ,  G06F9/3853

Abstract: A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.

Abstract translation: 计算机处理器的链接位解码器接收指令流。 链接位解码器从指令流中选择一组指令。 链接位解码器从指令流的每个指令中提取指定的位以产生一系列链接位。 链接位解码器解码链接序列。 考虑到解码的链接序列，链接位解码器识别所选择的指令组之中的零个或多个指令流相关性。 链接位解码器输出控制信号以使得处理器的一个或多个管线级鉴于所述组指令序列中所识别的零个或多个指令流依赖性来执行所选择的指令组。

公开(公告)号：US09558000B2

公开(公告)日：2017-01-31

申请号：US14539342

申请日：2014-11-12

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： C. John Glossner ,  Gary J. Nacer ,  Murugappan Senthilvelan ,  Vitaly Kalashnikov ,  Arthur J. Hoane ,  Paul D'Arcy ,  Sabin D. Iancu ,  Shenghong Wang

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3851 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/46

Abstract: A processing device identifies a set of software threads having instructions waiting to issue. For each software thread in the set of the software threads, the processing device binds the software thread to an available hardware context in a set of hardware contexts and stores an identifier of the available hardware context bound to the software thread to a next available entry in an ordered list. The processing device reads an identifier stored in an entry of the ordered list. Responsive to an instruction associated with the identifier having no dependencies with any other instructions among the instructions waiting to issue, the processing device issues the instruction waiting to issue to the hardware context associated with the identifier.

Abstract translation: 处理设备识别具有等待发布的指令的一组软件线程。 对于软件线程集合中的每个软件线程，处理设备将软件线程绑定到一组硬件上下文中的可用硬件上下文，并将绑定到软件线程的可用硬件上下文的标识符存储到下一个可用条目中 有序列表。 处理装置读取存储在有序列表的条目中的标识符。 响应于等待发布的指令中与标识符相关联的与任何其他指令无关的指令，处理设备发出等待发布到与标识符相关联的硬件上下文的指令。

公开(公告)号：US20150220347A1

公开(公告)日：2015-08-06

申请号：US14539342

申请日：2014-11-12

Applicant: Optimum Semiconductor Technologies, Inc.

Inventor： C. John Glossner ,  Gary J. Nacer ,  Murugappan Senthilvelan ,  Vitaly Kalashnikov ,  Arthur J. Hoane ,  Paul D'Arcy ,  Sabin D. Iancu ,  Shenghong Wang

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3885 ,  G06F9/46

Abstract: A processing device identifies a set of software threads having instructions waiting to issue. For each software thread in the set of the software threads, the processing device binds the software thread to an available hardware context in a set of hardware contexts and stores an identifier of the available hardware context bound to the software thread to a next available entry in an ordered list. The processing device reads an identifier stored in an entry of the ordered list. Responsive to an instruction associated with the identifier having no dependencies with any other instructions among the instructions waiting to issue, the processing device issues the instruction waiting to issue to the hardware context associated with the identifier.

Abstract translation: 处理设备识别具有等待发布的指令的一组软件线程。 对于软件线程集合中的每个软件线程，处理设备将软件线程绑定到一组硬件上下文中的可用硬件上下文，并将绑定到软件线程的可用硬件上下文的标识符存储到下一个可用条目中 有序列表。 处理装置读取存储在有序列表的条目中的标识符。 响应于等待发布的指令中与标识符相关联的与任何其他指令无关的指令，处理设备发出等待发布到与标识符相关联的硬件上下文的指令。