公开(公告)号：US20190102391A1

公开(公告)日：2019-04-04

申请号：US15943335

申请日：2018-04-02

Applicant: Oracle International Corporation

Inventor： Aurosish Mishra ,  Shasank K. Chavan ,  Vinita Subramanian ,  Ekrem S.C. Soylemez ,  Adam Kociubes ,  Eugene Karichkin ,  Garret F. Swart

IPC: G06F17/30

Abstract: Techniques related to cache storage formats are disclosed. In some embodiments, a set of values is stored in a cache as a set of first representations and a set of second representations. For example, the set of first representations may be a set of hardware-level representations, and the set of second representations may be a set of non-hardware-level representations. Responsive to receiving a query to be executed over the set of values, a determination is made as to whether or not it would be more efficient to execute the query over the set of first representations than to execute the query over the set of second representations. If the determination indicates that it would be more efficient to execute the query over the set of first representations than to execute the query over the set of second representations, the query is executed over the set of first representations.

公开(公告)号：US12093261B2

公开(公告)日：2024-09-17

申请号：US15943335

申请日：2018-04-02

Applicant: Oracle International Corporation

Inventor： Aurosish Mishra ,  Shasank K. Chavan ,  Vinita Subramanian ,  Ekrem S. C. Soylemez ,  Adam Kociubes ,  Eugene Karichkin ,  Garret F. Swart

IPC: G06F16/24 ,  G06F16/172 ,  G06F16/22 ,  G06F16/2455

CPC classification number: G06F16/24552 ,  G06F16/172 ,  G06F16/221 ,  G06F16/2455 ,  G06F16/24553

Abstract: Techniques related to cache storage formats are disclosed. In some embodiments, a set of values is stored in a cache as a set of first representations and a set of second representations. For example, the set of first representations may be a set of hardware-level representations, and the set of second representations may be a set of non-hardware-level representations. Responsive to receiving a query to be executed over the set of values, a determination is made as to whether or not it would be more efficient to execute the query over the set of first representations than to execute the query over the set of second representations. If the determination indicates that it would be more efficient to execute the query over the set of first representations than to execute the query over the set of second representations, the query is executed over the set of first representations.

公开(公告)号：US20170046128A1

公开(公告)日：2017-02-16

申请号：US15334349

申请日：2016-10-26

Applicant: Oracle International Corporation

Inventor： Jeffrey S. Brooks ,  Christopher H. Olson ,  Eugene Karichkin

IPC: G06F7/483 ,  G06F7/52 ,  G06F7/499

CPC classification number: G06F7/483 ,  G06F7/49947 ,  G06F7/52 ,  G06F2207/3816

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

Abstract translation: 公开了一种用于对可变长度和固定长度的机器独立数进行算术运算的处理器的实施例。 处理器可以包括浮点单元和逻辑电路。 数字单元可以被配置为接收操作，以及第一和第二操作数。 第一和第二操作数中的每一个可以包括符号字节和多个尾数字节，并且可以响应于操作数是固定长度数字的确定而被处理。 逻辑电路还可以被配置为对所处理的第一和第二操作数执行接收的操作。

公开(公告)号：US10180819B2

公开(公告)日：2019-01-15

申请号：US15334349

申请日：2016-10-26

Applicant: Oracle International Corporation

Inventor： Jeffrey S. Brooks ,  Christopher H. Olson ,  Eugene Karichkin

IPC: G06F7/483 ,  G06F7/499 ,  G06F7/52

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

公开(公告)号：US09507564B2

公开(公告)日：2016-11-29

申请号：US14251791

申请日：2014-04-14

Applicant: Oracle International Corporation

Inventor： Jeffrey S Brooks ,  Christopher H Olson ,  Eugene Karichkin

IPC: G06F7/483

CPC classification number: G06F7/483 ,  G06F7/49947 ,  G06F7/52 ,  G06F2207/3816

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

Abstract translation: 公开了一种用于对可变长度和固定长度的机器独立数进行算术运算的处理器的实施例。 处理器可以包括浮点单元和逻辑电路。 数字单元可以被配置为接收操作，以及第一和第二操作数。 第一和第二操作数中的每一个可以包括符号字节和多个尾数字节，并且可以响应于操作数是固定长度数字的确定而被处理。 逻辑电路还可以被配置为对所处理的第一和第二操作数执行接收的操作。

公开(公告)号：US20150293747A1

公开(公告)日：2015-10-15

申请号：US14251791

申请日：2014-04-14

Applicant: Oracle International Corporation

Inventor： Jeffrey S. Brooks ,  Christopher H. Olson ,  Eugene Karichkin

IPC: G06F7/483

CPC classification number: G06F7/483 ,  G06F7/49947 ,  G06F7/52 ,  G06F2207/3816

Abstract: Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

Abstract translation: 公开了一种用于对可变长度和固定长度的机器独立数进行算术运算的处理器的实施例。 处理器可以包括浮点单元和逻辑电路。 数字单元可以被配置为接收操作，以及第一和第二操作数。 第一和第二操作数中的每一个可以包括符号字节和多个尾数字节，并且可以响应于操作数是固定长度数字的确定而被处理。 逻辑电路还可以被配置为对所处理的第一和第二操作数执行接收的操作。