公开(公告)号：US10740102B2

公开(公告)日：2020-08-11

申请号：US15441411

申请日：2017-02-24

Applicant: Oracle International Corporation

Inventor： Munsefar Khaleque ,  Nathan Sheeley ,  Mark Greenberg ,  Matthew Smittle ,  Paul Jordan

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus includes an execution unit, an instruction queue, and a control circuit. The control circuit may be configured to activate a plurality of processor threads. Each of the plurality of processor threads may include a respective plurality of instructions. The instruction queue may be configured to issue at least one instruction included in the plurality of processor threads to the execution unit at a first rate. The control circuit may also be configured to track, for a particular processor thread, a period of time from activating the particular processor thread. The instruction queue may be further configured to limit issue of a next instruction for at least one other processor thread to a second rate, based on a comparison of the period of time to a threshold amount of time. The second rate may be lower than the first rate.

公开(公告)号：US20180246720A1

公开(公告)日：2018-08-30

申请号：US15441411

申请日：2017-02-24

Applicant: Oracle International Corporation

Inventor： Munsefar Khaleque ,  Nathan Sheeley ,  Mark Greenberg ,  Matthew Smittle ,  Paul Jordan

IPC: G06F9/30 ,  G06F9/38

Abstract: An apparatus includes an execution unit, an instruction queue, and a control circuit. The control circuit may be configured to activate a plurality of processor threads. Each of the plurality of processor threads may include a respective plurality of instructions. The instruction queue may be configured to issue at least one instruction included in the plurality of processor threads to the execution unit at a first rate. The control circuit may also be configured to track, for a particular processor thread, a period of time from activating the particular processor thread. The instruction queue may be further configured to limit issue of a next instruction for at least one other processor thread to a second rate, based on a comparison of the period of time to a threshold amount of time. The second rate may be lower than the first rate.