中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

13 records (took 0.021 seconds)

    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE
    2.
    发明申请
    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE 有权
    将CPU状态从不可操作的核心迁移到备用核心的方法

    公开(公告)号：US20160147534A1

    公开(公告)日：2016-05-26

    申请号：US14549742

    申请日：2014-11-21

    Applicant: Oracle International Corporation

    Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

    IPC: G06F9/30 ,  G06F12/08

    CPC classification number: G06F9/30145 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/2028 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2201/805 ,  G06F2212/452 ,  Y02D10/13

    Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

    Abstract translation: 公开了一种装置，其中装置可以包括多个芯，包括第一芯，第二芯和第三芯，以及耦合到第一芯的电路。 第一核可以被配置为处理多个指令。 电路可以被配置为检测第一核心停止提交多个指令的子集，并且向第二核心发送指示第一核心停止提交子集的指示。 第二核心可以被配置为响应于接收到指示而禁止第一核心进一步处理该子集的指令，并且响应于禁用第一核心将数据从第一核心复制到第三核心。 第三核可以被配置为依赖于数据来恢复处理该子集。

    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE
    3.
    发明申请
    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE 有权

    公开(公告)号：US20220156075A1

    公开(公告)日：2022-05-19

    申请号：US17648443

    申请日：2022-02-02

    Applicant: Oracle International Corporation

    Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

    IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0815 ,  G06F12/1027 ,  G06F9/38 ,  G06F9/48 ,  G06F3/06 ,  G06F11/20

    Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

    RANDOM NUMBER STORAGE, ACCESS, AND MANAGEMENT
    4.
    发明申请
    RANDOM NUMBER STORAGE, ACCESS, AND MANAGEMENT 有权
    随机数存储，访问和管理

    公开(公告)号：US20160328209A1

    公开(公告)日：2016-11-10

    申请号：US14706213

    申请日：2015-05-07

    Applicant: Oracle International Corporation

    Inventor： John Pape ,  Mark Luttrell ,  Paul Jordan ,  Michael Snyder

    IPC: G06F7/58

    CPC classification number: G06F7/58 ,  G06F7/582

    Abstract: Random numbers within a processor may be scarce, especially when multiple hardware threads are consuming them. A local random number buffer can be used by an execution core to better manage allocation and consumption of random numbers. The buffer may operate in a number of modes, and allow any hardware thread to use a random number under some conditions. In other conditions, only certain hardware threads may be allowed to consume a random number. The local random number buffer may have a dynamic pool of entries usable by any hardware thread, as well as reserved entries usable by only particular hardware threads. Further, a user-level instruction is disclosed that can be stored in a wait queue in response to a random number being unavailable, rather than having the instruction's request for a random number simply be denied. The random number buffer may also boost performance and reduce latency.

    Abstract translation: 处理器内的随机数可能很少，特别是当多个硬件线程消耗它们时。 执行核心可以使用本地随机数缓冲区来更好地管理随机数的分配和消耗。 缓冲器可以以多种模式操作，并且允许任何硬件线程在某些条件下使用随机数。 在其他条件下，只允许某些硬件线程使用随机数。 本地随机数缓冲器可以具有可由任何硬件线程使用的条目的动态池，以及仅由特定硬件线程使用的保留条目。 此外，公开了可以响应于随机数不可用而存储在等待队列中的用户级指令，而不是简单地拒绝指令对随机数的请求。 随机数缓冲器也可以提高性能并减少延迟。

    Storage, access, and management of random numbers generated by a central random number generator and dispensed to hardware threads of cores
    6.
    发明授权
    Storage, access, and management of random numbers generated by a central random number generator and dispensed to hardware threads of cores 有权

    公开(公告)号：US09971565B2

    公开(公告)日：2018-05-15

    申请号：US14706213

    申请日：2015-05-07

    Applicant: Oracle International Corporation

    Inventor： John Pape ,  Mark Luttrell ,  Paul Jordan ,  Michael Snyder

    IPC: G06F7/58

    CPC classification number: G06F7/58 ,  G06F7/582

    Abstract: Random numbers within a processor may be scarce, especially when multiple hardware threads are consuming them. A local random number buffer can be used by an execution core to better manage allocation and consumption of random numbers. The buffer may operate in a number of modes, and allow any hardware thread to use a random number under some conditions. In other conditions, only certain hardware threads may be allowed to consume a random number. The local random number buffer may have a dynamic pool of entries usable by any hardware thread, as well as reserved entries usable by only particular hardware threads. Further, a user-level instruction is disclosed that can be stored in a wait queue in response to a random number being unavailable, rather than having the instruction's request for a random number simply be denied. The random number buffer may also boost performance and reduce latency.

    Hardware mechanism to mitigate stalling of a processor core
    9.
    发明授权
    Hardware mechanism to mitigate stalling of a processor core 有权

    公开(公告)号：US10740102B2

    公开(公告)日：2020-08-11

    申请号：US15441411

    申请日：2017-02-24

    Applicant: Oracle International Corporation

    Inventor： Munsefar Khaleque ,  Nathan Sheeley ,  Mark Greenberg ,  Matthew Smittle ,  Paul Jordan

    IPC: G06F9/30 ,  G06F9/38

    Abstract: An apparatus includes an execution unit, an instruction queue, and a control circuit. The control circuit may be configured to activate a plurality of processor threads. Each of the plurality of processor threads may include a respective plurality of instructions. The instruction queue may be configured to issue at least one instruction included in the plurality of processor threads to the execution unit at a first rate. The control circuit may also be configured to track, for a particular processor thread, a period of time from activating the particular processor thread. The instruction queue may be further configured to limit issue of a next instruction for at least one other processor thread to a second rate, based on a comparison of the period of time to a threshold amount of time. The second rate may be lower than the first rate.

    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE
    10.
    发明申请
    METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE 审中-公开

    公开(公告)号：US20170293539A1

    公开(公告)日：2017-10-12

    申请号：US15632567

    申请日：2017-06-26

    Applicant: Oracle International Corporation

    Inventor： James Lewis ,  Paul Jordan ,  Gregory Onufer ,  Ali Vahidsafa

    IPC: G06F11/20 ,  G06F9/30 ,  G06F3/06

    Abstract: An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.

Patent Agency Ranking