公开(公告)号：US20060031274A1

公开(公告)日：2006-02-09

申请号：US10914554

申请日：2004-08-09

申请人： Osama Haddadin ,  Brad Hansen ,  L. Gibson ,  Roland Henrie

发明人： Osama Haddadin ,  Brad Hansen ,  L. Gibson ,  Roland Henrie

IPC分类号： G06F17/10

CPC分类号： H03H17/0277 ,  H03H17/0275 ,  H03H17/0657 ,  H03H17/0664 ,  H04L27/2631

摘要： A block polyphase filter is constructed of a set of filter blocks having different filter functions, and being arranged for parallel processing of portions of an input sequence of signals. Signals of the input sequence are divided among the blocks by a demultiplexer for processing at a clock frequency lower than a clock frequency of the input signal sequence. The filter blocks are arranged in groups, wherein output signals of the blocks in any one group are summed to produce an output signal of the filtered group. Output signals of all of the filter groups are multiplexed to provide an output signal sequence wherein the repetition frequency of the signals may be higher, lower, or equal to the repetition frequency of the input signal sequence depending upon the ratio of the number of filter groups to the number of filter blocks in the set of filter blocks.

摘要翻译： 块多相滤波器由具有不同滤波器功能的一组滤波器块构成，并被布置用于并行处理输入信号序列的部分。 输入序列的信号由解复用器在块之间分割，以便在低于输入信号序列的时钟频率的时钟频率处理。 滤波器块被分组布置，其中将任一组中的块的输出信号相加以产生滤波组的输出信号。 所有滤波器组的输出信号被复用以提供输出信号序列，其中信号的重复频率可以更高，更低或等于输入信号序列的重复频率，这取决于滤波器组的数量 到滤波器块集合中的滤波器块的数量。

公开(公告)号：US20050286619A1

公开(公告)日：2005-12-29

申请号：US10878902

申请日：2004-06-28

申请人： Osama Haddadin ,  Brad Hansen ,  David Nelson ,  Roland Henrie

发明人： Osama Haddadin ,  Brad Hansen ,  David Nelson ,  Roland Henrie

IPC分类号： H04B1/28 ,  H04B1/38

CPC分类号： H04B1/0092 ,  H04B1/0003 ,  H04B1/28 ,  H04L7/0029 ,  H04L7/0332

摘要： A demodulator, suitable for use in a communication system and in a modem, has a block polyphase circuit with circuit blocks for different signal processing functions, particularly filtering, delay, and frequency conversion. The circuit blocks are arranged for parallel processing of different portions of an input sequence of signals. Signals of the input sequence to be filtered are divided among the blocks by a demultiplexer for processing at a clock frequency lower than a clock frequency of the input signal sequence. Signals outputted by groups of the circuit blocks are summed to produce an output signal of the group. Frequency and timing reference signals, as well as fractional delay interpolation, are produced also by parallel-channel circuitry. Output signals of all of the groups are multiplexed to provide an output signal sequence such that the repetition frequency of the outputted signals may be higher, lower, or equal to that of the input signal sequence. This enables use of programmable circuitry operative at clock rates lower than rates required to process directly the input signal sequence.

摘要翻译： 适用于通信系统和调制解调器的解调器具有块多相电路，具有用于不同信号处理功能的电路块，特别是滤波，延迟和频率转换。 电路块被布置用于对输入信号序列的不同部分进行并行处理。 要被滤波的输入序列的信号由解复用器在块之间划分，以在低于输入信号序列的时钟频率的时钟频率处理。 将由电路块的组输出的信号相加以产生该组的输出信号。 频率和定时参考信号以及分数延迟插值也由并行通道电路产生。 所有组的输出信号被复用以提供输出信号序列，使得输出信号的重复频率可以高于，低于或等于输入信号序列的重复频率。 这使得可以使用以低于直接处理输入信号序列所需的速率的时钟速率工作的可编程电路。