公开(公告)号：US06191967B1

公开(公告)日：2001-02-20

申请号：US09314880

申请日：1999-05-19

申请人： Osamu Katayama ,  Takahiro Iwamura ,  Tetsuo Hirano

发明人： Osamu Katayama ,  Takahiro Iwamura ,  Tetsuo Hirano

IPC分类号： H02M7538

CPC分类号： H02M7/53803 ,  G01R31/40

摘要： A device selectively supplying a high voltage and a ground level voltage to electrodes of an electroluminescent display panel. The voltage supply device includes a first and a second transistor connected in series, and outputs the high voltage upon turning on the first switching transistor and the ground level voltage upon turning on the second switching transistor. The device includes a circuit for selecting either an operation mode under which the device is normally operated with the high voltage or a test mode under which the device is tested under a low test voltage. The mode selection is performed by an external signal supplied to the device. Under the test mode, the switching transistors are turned on with a low gate voltage by operation of a circuit built in the device. Accordingly, the voltage supply device normally operated under the high voltage is easily tested under the low test voltage.

摘要翻译： 选择性地向电致发光显示面板的电极提供高电压和地电平电压的装置。 电压供给装置包括串联连接的第一和第二晶体管，并且在接通第二开关晶体管时，在接通第一开关晶体管时输出高电压和接地电平电压。 该器件包括用于选择器件正常工作在高电压下的操作模式的电路或在低测试电压下对器件进行测试的测试模式。 模式选择由提供给设备的外部信号执行。 在测试模式下，开关晶体管通过内置在器件中的电路的操作以低栅极电压导通。 因此，在低电压下正常工作的电压供给装置容易测试。

公开(公告)号：US5812022A

公开(公告)日：1998-09-22

申请号：US715610

申请日：1996-09-18

申请人： Tetsuo Hirano ,  Ryuichirou Abe ,  Hiroaki Tanaka

发明人： Tetsuo Hirano ,  Ryuichirou Abe ,  Hiroaki Tanaka

IPC分类号： H03F1/26 ,  H03F3/45

CPC分类号： H03F3/45076

摘要： A differential amplifier circuit whose noise is reduced when used in a CMOS operational amplifier without increasing its cost includes a differential input stage circuit in which gate lengths of load transistors and gate lengths of differential input transistors are set to an optimal ratio to minimize internal transistor noise components.

摘要翻译： 在不增加成本的情况下，在CMOS运算放大器中使用噪声降低的差分放大器电路包括差分输入级电路，其中负载晶体管的栅极长度和差分输入晶体管的栅极长度被设置为使最小化内部晶体管噪声的最佳比率 组件。

公开(公告)号：US5495199A

公开(公告)日：1996-02-27

申请号：US309499

申请日：1994-09-23

申请人： Tetsuo Hirano

发明人： Tetsuo Hirano

IPC分类号： H03H19/00 ,  G06G7/186 ,  H03K17/16

CPC分类号： G06G7/1865 ,  H03H19/004

摘要： A switched capacitor circuit includes a capacitor, a MOS switch and a timing generating circuit. The MOS switch is connected with the capacitor in series for discharging electric charges which are charged into the capacitor. The MOS switch includes a plurality of MOS transistors which are parallelly connected with each other. The timing generating circuit generates timing signals to the MOS switch so that the MOS transistors are turned on one after another in response to each timing signal. Sampling noise is reduced because an ON-state resistance of the MOS switch is transiently high.

摘要翻译： 开关电容电路包括电容器，MOS开关和定时发生电路。 MOS开关与电容器串联连接，用于放电充入电容器的电荷。 MOS开关包括彼此并联连接的多个MOS晶体管。 定时产生电路产生到MOS开关的定时信号，使得MOS晶体管响应于每个定时信号一个接一个地接通。 由于MOS开关的导通电阻瞬时高，所以采样噪声降低。

公开(公告)号：US5422854A

公开(公告)日：1995-06-06

申请号：US104912

申请日：1993-08-12

申请人： Tetsuo Hirano ,  Takahiro Yanagi ,  Hiroaki Tanaka

发明人： Tetsuo Hirano ,  Takahiro Yanagi ,  Hiroaki Tanaka

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C16/28

摘要： Output signals, representing data read out from a memory cell array comprising a plurality of memory cells arranged in a matrix of m rows and n columns, each cell comprising an EPROM transistor, are fed to a sense amplifier. A row of the memory cell array is selected by signals SRl-SRm coming from a row decoder. The output of the selected row is taken out by a column select transistor selected by signals SCl-SCn from a column decoder before being fed to the sense amplifier. The sense amplifier comprises a memory cell output detecting circuit having a first load transistor for receiving output read out from the memory cell array and a dummy cell output detecting circuit having a second load transistor to which dummy cell equivalent to the memory cell is connected. The circuit of the first load transistor and that of the second load transistor form a current mirror circuit. The sense amplifier also comprises a sense amplifier output evaluation circuit having differential amplifiers which transmit output voltages of the memory cell output detecting circuit and of the dummy cell output detecting circuit to reflect the respective currents running through the first and second load transistors.

摘要翻译： 输出信号，表示从包括以m行和n列的矩阵排列的多个存储单元的存储单元阵列读出的数据，每个单元包括EPROM晶体管，被馈送到读出放大器。 存储单元阵列的一行由来自行解码器的信号SR1-SRm选择。 所选行的输出在被馈送到读出放大器之前由列解码器由信号SCl-SCn选择的列选择晶体管取出。 读出放大器包括：存储单元输出检测电路，具有用于接收从存储单元阵列读出的输出的第一负载晶体管;以及具有第二负载晶体管的虚设单元输出检测电路，虚拟单元与该存储单元相连。 第一负载晶体管和第二负载晶体管的电路形成电流镜电路。 读出放大器还包括具有差分放大器的读出放大器输出评估电路，差分放大器传输存储单元输出检测电路和虚拟单元输出检测电路的输出电压，以反映通过第一和第二负载晶体管流过的相应电流。