公开(公告)号：US12262049B2

公开(公告)日：2025-03-25

申请号：US18545682

申请日：2023-12-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N11/02 ,  H04N19/119 ,  H04N19/176 ,  H04N19/52

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in operation, selects an encoding mode from among candidates including a decoder-side motion vector refinement (DMVR) encoding mode and a partition encoding mode. When the DMVR encoding mode is selected, the circuitry: obtains a first motion vector for a first image block; derives a second motion vector from the first motion vector using motion search; and generates a prediction image for the first image block using the second motion vector. When the partition encoding mode is selected, the circuitry: determines a plurality of partitions in a second image block; obtains a third motion vector for each partition; and generates a prediction image for the second image block using the third motion vector, without deriving a fourth motion vector from the third motion vector using motion search.

公开(公告)号：US12262004B2

公开(公告)日：2025-03-25

申请号：US17582950

申请日：2022-01-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Che-Wei Kuo ,  Chong Soon Lim ,  Jing Ya Li ,  Han Boon Teo ,  Hai Wei Sun ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/117 ,  H04N19/132 ,  H04N19/159 ,  H04N19/176 ,  H04N19/186 ,  H04N19/82

Abstract: An encoder includes circuitry which generates a first coefficient value by applying a CCALF process to a first reconstructed image sample of a luma component; generates a second coefficient value by applying an ALF process to a second reconstructed image sample of a chroma component; generates a third coefficient value by adding the first coefficient value to the second coefficient value; and encodes a third reconstructed image sample of the chroma component using the third coefficient value. The circuitry writes a first parameter into a sequence parameter set; writes a second parameter into a parameter set of a picture in response to a value of the first parameter being 1; writes a third parameter into a slice header in response to the value of the first parameter being 1; and writes a fourth parameter into a coding tree unit in response to a value of the third parameter being 1.

公开(公告)号：US12244797B2

公开(公告)日：2025-03-04

申请号：US18516252

申请日：2023-11-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/117 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186

Abstract: An encoder includes processing circuitry and a memory coupled to the processing circuitry. Using the memory, the processing circuitry is configured to: change values of pixels in a first block and a second block to filter a boundary between the first block and the second block. The pixels include type one pixels and type two pixels different from the type one pixels. The first set of filter coefficients applied to the type one pixels in the first block and the second set of filter coefficients applied to the type one pixels in the second block are selected to be asymmetrical with respect to the boundary.

公开(公告)号：US20250047899A1

公开(公告)日：2025-02-06

申请号：US18921409

申请日：2024-10-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/52 ,  H04N19/176 ,  H04N19/186

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: stores MV information and correction processing information into a FIFO buffer for an HMVP mode in association, the MV information being derived for a processed block and correction processing information being related to correction processing of a prediction image of the processed block; registers, in a prediction candidate list for a merge mode, one or more prediction candidates each being a combination of MV information and correction processing information, the prediction candidates including a prediction candidate which is a combination of the motion vector information and the correction processing information stored in the FIFO buffer; and selects a prediction candidate from the prediction candidate list when a current block is to be processed in the merge mode, and performs correction processing of a prediction image of the current block, based on the correction processing information.

公开(公告)号：US12219155B2

公开(公告)日：2025-02-04

申请号：US18591350

申请日：2024-02-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/159 ,  H04N19/119 ,  H04N19/139 ,  H04N19/513

Abstract: An encoder encodes a video, and includes: circuitry; and memory coupled to the circuitry. Using the memory, the circuitry: obtains at least two items of prediction information for a first partition included in the video; derives at least one template from neighboring samples which neighbor the first partition; calculates at least two costs, using the at least one template and the at least two items of prediction information; using the at least two costs, (i) determines at least one splitting direction for the first partition or (ii) assigns one of the at least two items of prediction information to a second partition split from the first partition according to the splitting direction, and another thereof to a third partition split from the first partition according to the splitting direction; and encodes the first partition according to the splitting direction and the at least two items of prediction information.

公开(公告)号：US20250037315A1

公开(公告)日：2025-01-30

申请号：US18910149

申请日：2024-10-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Toshiyasu SUGIO ,  Takahiro Nishi ,  Tadamasa Toma ,  Toru Matsunobu ,  Satoshi Yoshikawa ,  Tatsuya Koyama

IPC: G06T9/00 ,  G01C21/00 ,  G01S17/89 ,  G06T17/05 ,  H04L67/01 ,  H04N13/275

Abstract: A three-dimensional data creation method in a client device includes: creating three-dimensional data of a surrounding area of the client device using sensor information that is obtained through a sensor equipped in the client device and indicates a surrounding condition of the client device; estimating a self-location of the client device using the three-dimensional data created; and transmitting the sensor information obtained to a server or an other client device.

公开(公告)号：US12206906B2

公开(公告)日：2025-01-21

申请号：US18484292

申请日：2023-10-10

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Che-Wei Kuo ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/119 ,  H04N19/176 ,  H04N19/593

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry determines whether to split a current luma virtual pipeline decoding unit (VPDU) into smaller blocks. When it is determined not to split the current luma VPDU into smaller blocks, the circuitry predicts a block of chroma samples without using luma samples. When it is determined to split the luma VPDU into smaller blocks, the circuitry predicts the block of chroma samples using luma samples. The circuitry encodes the block using the predicted chroma samples.

公开(公告)号：US20250024036A1

公开(公告)日：2025-01-16

申请号：US18903251

申请日：2024-10-01

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie DRUGEON ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/119 ,  H04N19/159 ,  H04N19/176

Abstract: A decoding method is a decoding method of decoding a current block of a video from a bitstream. The decoding method includes: decoding, from the bitstream, a prediction mode indicator indicating whether bi/uni mixed prediction is to be performed for the current block; decoding, from the bitstream, two instances of motion information for the current block; and when the prediction mode indicator indicates that the bi/uni mixed prediction is to be performed for the current block, (i) for a first partition, performing first prediction using one of the two instances, the first partition being part of the current block, the first prediction being uni-prediction, and (ii) for a second partition, performing second prediction using both of the two instances, the second partition being part of the current block, the second prediction being bi-prediction.

公开(公告)号：US12200270B2

公开(公告)日：2025-01-14

申请号：US17589419

申请日：2022-01-31

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Che-Wei Kuo ,  Chu Tong Wang ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/82 ,  H04N19/105 ,  H04N19/109 ,  H04N19/11 ,  H04N19/117 ,  H04N19/119 ,  H04N19/12 ,  H04N19/124 ,  H04N19/13 ,  H04N19/132 ,  H04N19/157 ,  H04N19/172 ,  H04N19/176 ,  H04N19/18 ,  H04N19/186 ,  H04N19/61

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component, and generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry modifies the first coefficient value by performing an arithmetic right shift by 7 bits on the first coefficient value. The circuitry generates a third coefficient value by adding the modified first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value.

公开(公告)号：US12200234B2

公开(公告)日：2025-01-14

申请号：US18515944

申请日：2023-11-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/31 ,  H04N19/117 ,  H04N19/172

Abstract: An encoder which encodes a video including a plurality of pictures includes circuitry and memory. Using the memory, the circuitry performs: encoding a first picture among the plurality of pictures; and performing (i) a first operation for encoding a parameter set for a second picture which follows the first picture in coding order among the plurality of pictures after encoding the first picture, and encoding the second picture after encoding the parameter set, or (ii) a second operation for encoding the second picture without encoding the parameter set after encoding the first picture. The circuitry performs the first operation when the second picture is a determined picture, in the performing of the first operation or the second operation.