公开(公告)号：US10553676B2

公开(公告)日：2020-02-04

申请号：US16245125

申请日：2019-01-10

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideki Mizuhara ,  Yoshihiro Matsushima ,  Shinichi Oohashi

IPC: H01L23/29 ,  H01L23/31 ,  H01L29/06 ,  H01L21/78 ,  B23K26/361 ,  H01L21/268

Abstract: In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture.

公开(公告)号：US10224397B2

公开(公告)日：2019-03-05

申请号：US15823245

申请日：2017-11-27

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Hideki Mizuhara ,  Yoshihiro Matsushima ,  Shinichi Oohashi

IPC: H01L29/06 ,  H01L21/268 ,  H01L21/78 ,  H01L23/29 ,  H01L23/31 ,  B23K26/361

Abstract: In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture.

公开(公告)号：US09865679B2

公开(公告)日：2018-01-09

申请号：US14880975

申请日：2015-10-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hideki Mizuhara ,  Yoshihiro Matsushima ,  Shinichi Oohashi

IPC: H01L29/06 ,  H01L23/29 ,  H01L23/31 ,  H01L21/78 ,  H01L21/268 ,  B23K26/361

CPC classification number: H01L29/0657 ,  B23K26/361 ,  H01L21/268 ,  H01L21/78 ,  H01L23/293 ,  H01L23/3142 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture.

公开(公告)号：US10903359B2

公开(公告)日：2021-01-26

申请号：US16488199

申请日：2019-01-17

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Chie Fujioka ,  Hiroshi Yoshida ,  Yoshihiro Matsushima ,  Hideki Mizuhara ,  Masao Hamasaki ,  Mitsuaki Sakamoto

IPC: H01L29/78 ,  H01L23/538 ,  H01L27/088

Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.

公开(公告)号：US10854744B2

公开(公告)日：2020-12-01

申请号：US16447100

申请日：2019-06-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshihiro Matsushima ,  Shigetoshi Sota ,  Eiji Yasuda ,  Toshikazu Imai ,  Ryosuke Okawa ,  Kazuma Yoshida ,  Ryou Kato

IPC: H01L23/15 ,  H01L29/78 ,  H01L27/088

Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 μm, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.