REDUCING BUFFER SIZE REQUIREMENTS IN AN ELECTRONIC REGISTRATION SYSTEM
    1.
    发明申请
    REDUCING BUFFER SIZE REQUIREMENTS IN AN ELECTRONIC REGISTRATION SYSTEM 有权
    减少电子注册系统中的缓冲大小要求

    公开(公告)号:US20110235946A1

    公开(公告)日:2011-09-29

    申请号:US12730347

    申请日:2010-03-24

    IPC分类号: G06K9/03

    摘要: What is disclosed is a novel system and method for reducing a size of a memory buffer used by an electronic registration correction system performing an electronic registration correction on a digital image. The present method uses column address segmentation to identify blocks of scanlines within a spatially mapped array of image pixels comprising a digital image. Advantageously, the present system and method reduces scanline buffer memory by a factor of 2n−1, where n is the number of column address segments. Buffering can be performed at almost any upstream location in the image path. The present method is well suited for high resolution imaging equipment where memory is constrained by design, cost, or space limitations.

    摘要翻译: 公开的是一种用于减小由数字图像执行电子登录校正的电子登记校正系统使用的存储器缓冲器的大小的新型系统和方法。 本方法使用列地址分割来识别包括数字图像的图像像素的空间映射阵列内的扫描线块。 有利地,本系统和方法将扫描线缓冲存储器减少2n-1倍,其中n是列地址段的数量。 可以在图像路径中的几乎任何上游位置执行缓冲。 本方法非常适用于高分辨率成像设备,其中存储器受到设计,成本或空间限制的限制。

    METHOD FOR DICING A SEMICONDUCTOR WAFER, A CHIP DICED FROM A SEMICONDUCTOR WAFER, AND AN ARRAY OF CHIPS DICED FROM A SEMICONDUCTOR WAFER
    2.
    发明申请
    METHOD FOR DICING A SEMICONDUCTOR WAFER, A CHIP DICED FROM A SEMICONDUCTOR WAFER, AND AN ARRAY OF CHIPS DICED FROM A SEMICONDUCTOR WAFER 有权
    一个半导体波片的方法,一个半导体波片的芯片和一个由半导体波导引出的晶片阵列

    公开(公告)号:US20110147898A1

    公开(公告)日:2011-06-23

    申请号:US12646590

    申请日:2009-12-23

    IPC分类号: H01L23/544 H01L21/268

    摘要: A method for dicing a semiconductor wafer, including: cutting a reference slot in a back main surface of the wafer; cutting a back slot in the back main surface, the back slot positioned with respect to the reference slot; determining a desired location for a chip edge with respect to the reference slot; and applying radiant energy in a path such that a series of reformed regions are formed within the wafer along the path. A crystalline structure of the wafer is modified in the series of reformed regions and an alignment of an edge of the laser is with respect to the desired location for the chip edge and in alignment with the back slot. The method includes separating the wafer along the series of reformed regions to divide portions of the wafer on either side of the series of reformed regions.

    摘要翻译: 一种用于切割半导体晶片的方法,包括:切割晶片的后主表面中的参考槽; 切割后主表面中的后槽,相对于参考槽定位的后槽; 确定芯片边缘相对于参考时隙的期望位置; 并且在路径中施加辐射能,使得沿着路径在晶片内形成一系列重整区。 在一系列重整区域中修改了晶片的晶体结构,并且激光器边缘的对准相对于芯片边缘的期望位置并与后槽对准。 该方法包括沿着一系列重整区域分离晶片以将晶片的部分划分在一系列重整区域的两侧。