公开(公告)号：US10380305B1

公开(公告)日：2019-08-13

申请号：US15273545

申请日：2016-09-22

Applicant: PDF Solutions, Inc.

Inventor： Yih-Yuh Doong ,  Sheng-Che Lin ,  Chia-Chi Lin ,  Hans Eisenmann ,  Cho-Si Huang ,  Tzupin Shen ,  Christopher Hess ,  Kimon Michaels

IPC: G06F9/455 ,  G06F17/50

Abstract: A method is disclosed for designing a test vehicle utilizing a layout of a real integrated circuit (IC) product. The method comprises: importing an original full-chip layout of the real IC product; partitioning the original full-chip layout into probe groups, each probe group comprising probe pads, and, a plurality of IC devices within an area of interest (AOI) having original routing interconnect for those IC devices; selecting a set of IC devices within the AOI; and, for the selected set of IC devices, using pattern extraction to remove the original routing interconnect, and create customized interconnect layers (CIL) to reconfigure connection between the individual IC devices. Incorporating the selected set of IC devices with the CIL into the original full-chip layout creates a modified full-chip layout such that a wafer fabricated using the modified full-chip layout comprises a real product with a built-in test vehicle.

公开(公告)号：US10410735B1

公开(公告)日：2019-09-10

申请号：US15441016

申请日：2017-02-23

Applicant: PDF Solutions, Inc.

Inventor： Yih-Yuh Doong ,  Chao-Hsiung Lin ,  Sheng-Che Lin ,  Shihpin Kuo ,  Tzupin Shen ,  Chia-Chi Lin ,  Kimon Michaels

IPC: G11C29/12 ,  G06F1/3206 ,  G06F13/28 ,  G11C29/48

Abstract: A memory-specific implementation of a test and characterization vehicle utilizes a design layout that is a modified version of the product mask. Specific routing is used to modify the product mask in order to facilitate memory cell characterization. This approach can be applied to any memory architecture with word-line and bit-line perpendicular or substantially perpendicular to each other, including but not limited to, volatile memories such as Static Random Access Memory (SRAM), Dynamic RAM (DRAM), non-volatile memory such as NAND Flash (including three-dimensional NAND Flash), NOR Flash, Phase-change RAM (PRAM), Ferroelectric RAM (FeRAM), Correlated electron RAM (CeRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), XPoint memory and the like.

公开(公告)号：US10096378B1

公开(公告)日：2018-10-09

申请号：US15441002

申请日：2017-02-23

Applicant: PDF Solutions, Inc.

Inventor： Yih-Yuh Doong ,  Chao-Hsiung Lin ,  Sheng-Che Lin ,  Shihpin Kuo ,  Tzupin Shen ,  Chia-Chi Lin ,  Kimon Michaels

IPC: G11C29/00 ,  G11C29/02 ,  H03K17/687 ,  G11C8/08

Abstract: A capacitance measurement test vehicle comprises multiple product layers which are used to build memories except interconnect layers, and one or more customized interconnect layers to connect memory-bit-line-under-tests (MBLUTs), memory-world-line-under-tests (MWLUTs) and memory-bit-cell-under-tests (MUTs). By introducing two transistors, one PMOS and one NMOS, at two opposite sides or the same side of a bit-line or a world-line, the capacitance of the bit-line or the world-line can be measured by a parametric tester. The PMOS device is for pumping in current, and the NMOS device is for draining out the current. By applying a non-overlapping clocked signal at the PMOS and NMOS transistors, the capacitance of bit-line, word-line and bit-cell can be measured as current signal. The PMOS and NMOS transistors are selected from on-chip transistors that are already in the memory design layout.