公开(公告)号：US20230068223A1

公开(公告)日：2023-03-02

申请号：US17800226

申请日：2020-02-19

申请人： PIERBURG GMBH

发明人： MIKA NUOTIO

IPC分类号： H01L23/051 ,  H01L23/367 ,  H01L23/538 ,  H01L25/07 ,  H01L23/532 ,  H01L23/495 ,  H01L23/31

摘要： An integrated semiconductor power transistor package includes a half-bridge electrical circuit with a negative voltage outer terminal of a high-side switch connected in series with a positive voltage outer terminal of a low-side switch, a first and a second substrate, and vertical spacers. The high and the low side switches include semiconductor power transistor dies connected electrically parallel. The first substrate has a cladding layer sinter bonded to one of the semiconductor power transistor dies to define the low-side power switch. The second substrate has a first cladding layer sinter bonded to one of the semiconductor power transistor dies to define the high-side power switch, and a second cladding layer. Vertical spacers sinter bond the semiconductor power transistor die on the first substrate to the second cladding layer. Vertical spacers also sinter bond the semiconductor power transistor die on the second substrate to the cladding layer.

公开(公告)号：US20240355753A1

公开(公告)日：2024-10-24

申请号：US18553211

申请日：2022-02-25

申请人： PIERBURG GMBH

发明人： MIKA NUOTIO ,  DIETER JELINEK ,  OGUZ DEMIR ,  PATRICK BAUER

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L23/36 ,  H01L23/495 ,  H01L25/16

CPC分类号： H01L23/5386 ,  H01L23/5385 ,  H01L25/162 ,  H01L23/36 ,  H01L23/49517 ,  H01L24/48 ,  H01L2224/48137 ,  H01L2224/48225

摘要： A power semiconductor package includes a first substrate assembly with power semiconductor dies, a second substrate assembly arranged parallel to the first substrate assembly, and source contacts. The second substrate assembly has a copper cladding layer which defines a source copper cladding layer circuit having a bonding area which, when mechanically contacted, provides an electrical connection to the source copper cladding layer circuit. Each of the source contacts provide an electrical connection between a source connection of one of the power semiconductor dies and the source copper cladding layer circuit. The source contacts are arranged at different distances from the bonding area of the source copper cladding layer circuit. The source copper cladding layer circuit also has an electrically isolating slot arranged between one of the source contacts which is closest to the bonding area of the source copper cladding layer circuit and the bonding area.

公开(公告)号：US20240178108A1

公开(公告)日：2024-05-30

申请号：US18553210

申请日：2022-02-25

申请人： PIERBURG GMBH

发明人： MIKA NUOTIO ,  OGUZ DEMIR ,  PATRICK BAUER

IPC分类号： H01L23/495 ,  H01L25/07

CPC分类号： H01L23/49562 ,  H01L23/49582 ,  H01L25/074

摘要： A power semiconductor package includes a first substrate assembly with a power semiconductor die defining a high-side power switch, a second substrate assembly arranged parallel to the first substrate assembly which has a power semiconductor die defining a low-side power switch, and a power terminal assembly. The power terminal assembly includes a power terminal substrate arranged between the first and the second substrate assembly, a high-side drain power terminal electrically connected to an electrical drain circuit of the high-side power switch, a low-side source power terminal electrically connected to an electrical source circuit of the low-side power switch, and a mid-point power terminal electrically connected to an electrical source circuit of the high-side power switch and to an electrical drain circuit of the low-side power switch. The high-side drain power terminal, the low-side source power terminal, and the mid-point power terminal are each arranged on the power terminal substrate.