公开(公告)号：US12125816B2

公开(公告)日：2024-10-22

申请号：US17342721

申请日：2021-06-09

申请人： Micron Technology, Inc.

发明人： Jong Sik Paek ,  Po Chih Yang

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L24/20 ,  H01L23/3107 ,  H01L24/19 ,  H01L24/48 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/211 ,  H01L2224/48147 ,  H01L2224/48225 ,  H01L2225/06506 ,  H01L2225/0651

摘要： A semiconductor device assembly is provided. The assembly includes a redistribution layer (RDL) including a plurality of external contacts on a first side and a plurality of internal contacts on a second side opposite the first side. The assembly further includes a first die at least partially embedded in the RDL and having an active surface between the first side and the second side of the RDL. The assembly further includes one or more second dies disposed over the controller die and the RDL, wherein the one or more second dies electrically coupled to the internal contacts. The assembly further includes an encapsulant at least partially encapsulating the one or more second dies.

公开(公告)号：US20240347487A1

公开(公告)日：2024-10-17

申请号：US18368640

申请日：2023-09-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaeean Lee ,  Dahee Kim ,  Taehoon Lee ,  Gyujin Choi

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L24/05 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/06 ,  H01L24/08 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/03462 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0601 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/1815

摘要： An upper redistribution wiring layer of a semiconductor package includes a protective layer provided on at least one upper insulating layer and having an opening that exposes at least a portion of an uppermost redistribution wiring among second redistribution wirings, and a bonding pad provided on the uppermost redistribution wiring through the opening. The bonding pad includes a first plating pattern formed on the uppermost redistribution wiring, the first plating pattern including a via pattern provided in the opening and a pad pattern formed on the via pattern to be exposed from the opening, a second plating pattern on the second plating pattern, and a third plating pattern on the second plating pattern.

公开(公告)号：US12119281B2

公开(公告)日：2024-10-15

申请号：US17394093

申请日：2021-08-04

申请人： Qorvo US, Inc.

发明人： Dylan Murdock

IPC分类号： H01L23/31 ,  H01L23/04 ,  H01L23/10 ,  H01L23/29 ,  H01L23/00 ,  H01L23/373

CPC分类号： H01L23/3142 ,  H01L23/04 ,  H01L23/10 ,  H01L23/291 ,  H01L23/315 ,  H01L23/3736 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48225 ,  H01L2224/49176 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/0132 ,  H01L2924/01403 ,  H01L2924/05432 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/15787 ,  H01L2924/16747 ,  H01L2924/1676 ,  H01L2924/173 ,  H01L2924/17747 ,  H01L2924/1776 ,  H01L2924/3512

摘要： The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

公开(公告)号：US20240321834A1

公开(公告)日：2024-09-26

申请号：US18734915

申请日：2024-06-05

申请人： FUJI ELECTRIC CO., LTD.

发明人： Mitsuhiro KAKEFU ,  Hiroaki ICHIKAWA

IPC分类号： H01L25/07 ,  H01L23/00 ,  H01L23/498 ,  H01L29/739 ,  H01L29/861

CPC分类号： H01L25/072 ,  H01L23/49844 ,  H01L24/48 ,  H01L29/7393 ,  H01L29/861 ,  H01L2224/48225

摘要： A semiconductor device having a semiconductor unit including: a first arm part that includes first and second semiconductor chips respectively having first and second main electrodes, a first circuit pattern on which the first and second semiconductor chips are disposed, a second circuit pattern, a first main current wire connecting the first main electrode and second circuit pattern, and a second main current wire connecting the second main electrode and the second circuit pattern; and a second arm part that includes third and fourth semiconductor chips respectively having third and fourth main electrodes and being disposed on the second circuit pattern, a third circuit pattern, a third main current wire connecting the third main electrode and the third circuit pattern, and a fourth main current wire connecting the fourth main electrode and the third circuit pattern. Each semiconductor chip is an IGBT or MOSFET.

公开(公告)号：US20240304515A1

公开(公告)日：2024-09-12

申请号：US18357211

申请日：2023-07-24

申请人： Western Digital Technologies, Inc.

发明人： Xuyi Yang ,  Yiqin Huang ,  Zengyu Zhou ,  Kandy Sun ,  Jerry Tang ,  Gang Liu ,  Cong Zhang ,  Hope Chiu

IPC分类号： H01L23/373 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/3735 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/73204 ,  H01L2225/065 ,  H01L2924/1438 ,  H10B80/00

摘要： A semiconductor package having various thermal dissipation features to dissipate heat. The semiconductor package may include an integrated circuit and a non-volatile storage device. Vias may be formed in the substrate and filled with a thermal conductive material. A pyrolytic graphite sheet overlays a top surface of the substrate and the vias. The pyrolytic graphite sheet defines one or more openings that enable the integrated circuit and the non-volatile storage device to be coupled to the top surface of the substrate. The integrated circuit is covered by another thermal conductive material such as a copper or silver paste. The copper or silver paste also covers a sidewall of the pyrolytic graphite sheet. The semiconductor package is enclosed by molding material and a metal layer. The pyrolytic graphite sheet connects the metal layer and the thermal conductive material overlaying the integrated circuit to form various thermal dissipation paths.

公开(公告)号：US12087699B2

公开(公告)日：2024-09-10

申请号：US17609885

申请日：2020-04-22

申请人： Danfoss Silicon Power GmbH

发明人： Alvaro Jorge Mari Curbelo ,  Tobias Schütz ,  Robert Rösner

IPC分类号： H01L23/498 ,  H01L23/538 ,  H01L25/07 ,  H01L23/00 ,  H02M7/00 ,  H02M7/537

CPC分类号： H01L23/5386 ,  H01L25/072 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48225 ,  H01L2224/49175 ,  H02M7/003 ,  H02M7/537

摘要： A power module (1) providing a half bridge, the power module including: at least one substrate (2) including an inner load track (3), two intermediate load tracks (4) and two outer load tracks (5), each of which load tracks is elongated and extends substantially across the at least one substrate (2) in a first direction (6); wherein the two intermediate load tracks (4) are arranged adjacent to the inner load track (3), and each outer load track (5) is arranged on the opposite side of one of the two intermediate load tracks (4) with respect to a second direction (7) substantially orthogonal to the first direction (6).

公开(公告)号：US20240297096A1

公开(公告)日：2024-09-05

申请号：US18239126

申请日：2023-08-29

申请人： JMJ Korea Co., Ltd.

发明人： Yun Hwa CHOI

IPC分类号： H01L23/473 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/473 ,  H01L23/49811 ,  H01L23/49866 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/48105 ,  H01L2224/48225 ,  H01L2225/06503 ,  H01L2924/365

摘要： The present invention relates to a semiconductor package having a heat emitting post bonded thereto and a method of manufacturing the same, and more particularly, to a semiconductor package having a heat emitting post bonded thereto and a method of manufacturing the same that may increase bond strength of the heat emitting post and improve durability of bonding members contacting cooling water.

公开(公告)号：US20240266254A1

公开(公告)日：2024-08-08

申请号：US18563120

申请日：2021-06-01

申请人： Peking University

发明人： Wei WANG ,  Yuchi YANG ,  Jianyu DU

IPC分类号： H01L23/473 ,  H01L21/48 ,  H01L23/00

CPC分类号： H01L23/473 ,  H01L21/4853 ,  H01L24/48 ,  H01L2224/48225

摘要： The present invention relates to a wire bonding structure with an embedded manifold type micro-channel. The wire bonding structure includes: a chip, including a substrate and an embedded micro-channel located on a back portion of the substrate; an interposer, including a manifold channel, a liquid inlet, and a liquid outlet; a low-temperature sealing layer, configured to hermetically communicate the embedded micro-channel with the manifold channel, wherein the low-temperature sealing layer is located between the chip and the interposer; and a bonding wire, configured to electrically connect the chip to the interposer. The present invention further relates to a preparation method of a wire bonding structure with an embedded manifold type micro-channel. The wire bonding structure of the present invention has both low-temperature process compatibility and packaging compatibility, and further has high heat dissipation efficiency. The embedded manifold type micro-channel of the present invention has the advantages of short flow distance, low flow resistance, and low thermal resistance, and is more suitable for being integrated into a high-power chip for efficient heat dissipation.

公开(公告)号：US20240250009A1

公开(公告)日：2024-07-25

申请号：US18158225

申请日：2023-01-23

申请人： QUALCOMM Incorporated

发明人： Seongryul Choi ,  Joan Rey Villarba Buot ,  Kuiwon Kang ,  Zhijie Wang

IPC分类号： H01L23/498 ,  H01L21/288 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/49838 ,  H01L21/288 ,  H01L21/76829 ,  H01L23/49816 ,  H01L24/04 ,  H01L24/08 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/08112 ,  H01L2224/08225 ,  H01L2224/16014 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/48105 ,  H01L2224/48225

摘要： Embedded trace substrates (ETS) having an ETS metallization layer with T-shaped interconnects with reduced-width embedded metal traces, and related integrated circuit (IC) packages and fabrication methods. The ETS includes an outer ETS metallization layer that includes T-shaped interconnects for supporting input/output (I/O) connections between the ETS and another opposing package substrate. To increase density of I/O interconnections, the pitch of the embedded metal traces in the ETS metallization layer is reduced. The T-shaped interconnects also each include an additional metal contact pad that is coupled to a respective embedded metal trace to increase the height of the embedded metal trace to eliminate a vertical connection gap between the ETS and an opposing package substrate. In the T-shape interconnects, their embedded metal traces are reduced in width in a horizontal direction(s) as compared to their respective metal contact pads to provide room for additional metal traces for additional signal routing capacity.

公开(公告)号：US12046549B2

公开(公告)日：2024-07-23

申请号：US17765756

申请日：2020-10-21

申请人： ROHM CO., LTD.

发明人： Maiko Hatano

IPC分类号： H01L23/498 ,  H01L23/00 ,  H01L23/14 ,  H01L25/07

CPC分类号： H01L23/49844 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/32 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L25/072 ,  H01L24/16 ,  H01L2224/16245 ,  H01L2224/32225 ,  H01L2224/4001 ,  H01L2224/40095 ,  H01L2224/40177 ,  H01L2224/40225 ,  H01L2224/48225 ,  H01L2224/73207 ,  H01L2224/73221 ,  H01L2224/73253 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2924/10272 ,  H01L2924/13091 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/3511

摘要： A semiconductor device includes an insulating substrate, a first and a second obverse-surface metal layers disposed on an obverse surface of the insulating substrate, a first and a second reverse-surface metal layers disposed on a reverse surface of the insulating substrate, a first conductive layer and a first semiconductor element disposed on the first obverse-surface metal layer, and a second conductive layer and a second semiconductor element disposed on the second obverse-surface metal layer. Each of the first conductive layer and the second conductive layer has an anisotropic coefficient of linear expansion and is arranged such that the direction in which the coefficient of linear expansion is relatively large is along a predetermined direction perpendicular to the thickness direction of the insulating substrate. The first and second reverse-surface metal layers are smaller than the first and second obverse-surface metal layers in dimension in the predetermined direction.