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    Transitioning digital data processors between power savings and non-power savings modes
    1.
    发明授权
    Transitioning digital data processors between power savings and non-power savings modes 有权
    在省电和非节电模式之间转换数字数据处理器

    公开(公告)号：US08242940B2

    公开(公告)日：2012-08-14

    申请号：US12966045

    申请日：2010-12-13

    申请人： Pablo Ventura Domingo ,  Lucas Valentin Garcia ,  Michael Joseph Fernald ,  Rajesh Rama Chandran ,  Joseph Michael Barry

    发明人： Pablo Ventura Domingo ,  Lucas Valentin Garcia ,  Michael Joseph Fernald ,  Rajesh Rama Chandran ,  Joseph Michael Barry

    IPC分类号： H03M9/00

    CPC分类号： G06F1/3278 ,  Y02D10/157 ,  Y02D50/20

    摘要： A sink may be to used to process multimedia digital data. The sink may include a plurality of input ports, an output port, a switchably-enabled selector to select an input port from a plurality of HDMI input ports to couple to an output port, a control circuit to detect encrypted data in a channel of the input ports; and a plurality of decryption engines. Each of the decryption engines may be coupled to respective input ports to synchronize with a corresponding encryption engine of a data source after the control circuit detects encrypted data in the channel of the respective input port. Additional circuitry may be included to operate the sink in a power saving mode. Also, methods for processing the data in both power saving and non-power saving modes.

    摘要翻译： 宿槽可用于处理多媒体数字数据。 接收器可以包括多个输入端口，输出端口，可切换使能的选择器，用于从多个HDMI输入端口选择输入端口以耦合到输出端口;控制电路，用于检测信道中的加密数据 输入端口; 和多个解密引擎。 在控制电路检测到相应输入端口的通道中的加密数据之后，每个解密引擎可以耦合到相应的输入端口，以与数据源的对应加密引擎同步。 可以包括额外的电路来以省电模式操作接收器。 另外，在省电模式和非省电模式下处理数据的方法。

    Fast switching between digital video sources
    2.
    发明授权
    Fast switching between digital video sources 有权
    快速切换数字视频源

    公开(公告)号：US08331561B2

    公开(公告)日：2012-12-11

    申请号：US12966146

    申请日：2010-12-13

    申请人： Pablo Ventura Domingo ,  Lucas Valentin Garcia ,  Michael Joseph Fernald ,  Rajesh Rama Chandran ,  Joseph Michael Barry

    发明人： Pablo Ventura Domingo ,  Lucas Valentin Garcia ,  Michael Joseph Fernald ,  Rajesh Rama Chandran ,  Joseph Michael Barry

    IPC分类号： H04L9/00

    CPC分类号： H04N21/4367 ,  G09G5/006 ,  G09G2330/021 ,  G09G2358/00 ,  G09G2370/12 ,  G09G2370/20 ,  H04N7/1675 ,  H04N21/43632

    摘要： A sink may be to used to process multimedia digital data. The sink may include a plurality of input ports, an output port, a switchably-enabled selector to select an input port from a plurality of HDMI input ports to couple to an output port, a control circuit to detect encrypted data in a channel of the input ports; and a plurality of decryption engines. Each of the decryption engines may be coupled to respective input ports to synchronize with a corresponding encryption engine of a data source after the control circuit detects encrypted data in the channel of the respective input port. Additional circuitry may be included to operate the sink in a power saving mode. Also, methods for processing the data in both power saving and non-power saving modes.

    摘要翻译： 宿槽可用于处理多媒体数字数据。 接收器可以包括多个输入端口，输出端口，可切换使能的选择器，用于从多个HDMI输入端口选择输入端口以耦合到输出端口;控制电路，用于检测信道中的加密数据 输入端口; 和多个解密引擎。 在控制电路检测到相应输入端口的通道中的加密数据之后，每个解密引擎可以耦合到相应的输入端口，以与数据源的对应加密引擎同步。 可以包括额外的电路来以省电模式操作接收器。 另外，在省电模式和非省电模式下处理数据的方法。

    Digital signal processor optimized for interpolation and decimation
    4.
    发明授权
    Digital signal processor optimized for interpolation and decimation 有权
    针对插值和抽取优化的数字信号处理器

    公开(公告)号：US07702710B2

    公开(公告)日：2010-04-20

    申请号：US11224495

    申请日：2005-09-12

    申请人： Pablo Ventura Domingo

    发明人： Pablo Ventura Domingo

    IPC分类号： G06F17/17

    CPC分类号： H03H17/0621 ,  H03H2017/0298 ,  H03H2218/08

    摘要： A digital signal processor receives samples of a first digital signal which is to be decimated and samples of a second digital signal which is to be interpolated. A digital signal processing engine performs a decimation function on samples of the first digital signal and an interpolation function on samples of the second digital signal on a time-shared basis. The digital signal processor has a first dual memory space for storing the samples of the first digital signal and a second dual memory space for storing the samples of the second digital signal. Outputs retrieved from a dual memory space are pre-added and applied to a multiplication and accumulation stage which operates on the pre-added outputs and a filter coefficient of a digital filter.

    摘要翻译： 数字信号处理器接收要抽取的第一数字信号的样本和要被内插的第二数字信号的采样。 数字信号处理引擎在时间共享的基础上对第一数字信号的采样和对第二数字信号的采样执行内插函数执行抽取功能。 数字信号处理器具有用于存储第一数字信号的采样的第一双存储器空间和用于存储第二数字信号的采样的第二双存储器空间。 从双存储器空间检索的输出被预先添加并应用于对预加输出进行操作的乘法和累加阶段以及数字滤波器的滤波器系数。