公开(公告)号：US12301804B2

公开(公告)日：2025-05-13

申请号：US18417952

申请日：2024-01-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Ryuichi Kanoh ,  Chong Soon Lim ,  Ru Ling Liao ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Jing Ya Li

IPC: H04N19/119 ,  H04N19/137 ,  H04N19/176 ,  H04N19/52

Abstract: Provided is an encoder which includes circuitry and memory. Using the memory, the circuitry splits an image block into a plurality of partitions, obtains a prediction image for a partition, and encodes the image block using the prediction image. When the partition is not a non-rectangular partition, the circuitry obtains (i) a first prediction image for the partition, (ii) a gradient image for the first prediction image, and (iii) a second prediction image as the prediction image using the first prediction image and the gradient image. When the partition is a non-rectangular partition, the circuitry obtains the first prediction image as the prediction image without using the gradient image.

公开(公告)号：US12301796B2

公开(公告)日：2025-05-13

申请号：US18539753

申请日：2023-12-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya Li ,  Ru Ling Liao ,  Chong Soon Lim ,  Han Boon Teo ,  Hai Wei Sun ,  Che Wei Kuo ,  Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/105 ,  H04N19/136 ,  H04N19/159 ,  H04N19/176 ,  H04N19/52 ,  H04N19/80

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of horizontal gradient values; derives, as a first parameter, the total sum of the absolute values of horizontal gradient values; derives, as a second parameter, the total sum of the absolute values of vertical gradient values; derives a horizontal-related pixel difference value; derives, as a third parameter, the total sum of the absolute values of horizontal-related pixel difference values; derives a vertical-related pixel difference value; derives, as a fourth parameter, the total sum of the absolute values of vertical-related pixel difference values; and generates a prediction image using the first to fourth parameters.

公开(公告)号：US12244796B2

公开(公告)日：2025-03-04

申请号：US18510427

申请日：2023-11-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe

IPC: H04N19/117 ,  H04N19/146 ,  H04N19/176

Abstract: A decoder comprises circuitry and memory. The circuitry, using the memory, in operation, determines a number of first pixels and a number of second pixels used in a deblocking filter process, wherein the first pixels are located at an upper side of a block boundary and the second pixels are located at a lower side of the block boundary, and performs the deblocking filter process on the block boundary. The number of the first pixels and the number of the second pixels are selected from among candidates, wherein the candidates include at least 4 and M larger than 4. Response to a location of the block boundary being a predetermined location, the number of the first pixels used in the deblocking filter process is limited to be 4.

公开(公告)号：US12225220B2

公开(公告)日：2025-02-11

申请号：US17684657

申请日：2022-03-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke Kato

IPC: H04N19/423 ,  H04N19/159 ,  H04N19/176 ,  H04N19/82

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry determines one or more tiles included in a picture and one or more subpictures included in the picture, according to a constraint condition that each tile of the one or more tiles includes at least one subpicture of the one or more subpictures entirely and the each tile does not include another subpicture of the one or more subpictures partially.

公开(公告)号：US12177438B2

公开(公告)日：2024-12-24

申请号：US18311064

申请日：2023-05-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/124 ,  H04N19/136 ,  H04N19/157 ,  H04N19/176 ,  H04N19/61

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, the circuitry: performs quantization on a plurality of transform coefficients of a current block to be encoded, using a quantization matrix when orthogonal transform is performed on the current block and secondary transform is not performed on the current block; and performs quantization on the plurality of transform coefficients of the current block without using the quantization matrix when orthogonal transform is not performed on the current block and when both orthogonal transform and secondary transform are performed on the current block.

公开(公告)号：US12160600B2

公开(公告)日：2024-12-03

申请号：US18331800

申请日：2023-06-08

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Sughosh Pavan Shashidhar ,  Ru Ling Liao ,  Hai Wei Sun ,  Han Boon Teo ,  Jing Ya Li ,  Kiyofumi Abe ,  Tadamasa Toma ,  Takahiro Nishi

IPC: H04N19/44 ,  H04N19/119 ,  H04N19/137 ,  H04N19/159 ,  H04N19/176

Abstract: An image decoder has circuitry coupled to a memory. The circuitry splits a current image block into a plurality of partitions. The circuitry predicts a first motion vector from a set of uni-prediction motion vector candidates for a first partition of the plurality of partitions, and decodes the first partition using the first motion vector.

公开(公告)号：US12149745B2

公开(公告)日：2024-11-19

申请号：US17834194

申请日：2022-06-07

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe ,  Yusuke Kato

IPC: H04N19/70 ,  H04N19/105 ,  H04N19/154 ,  H04N19/169 ,  H04N19/172 ,  H04N19/29 ,  H04N19/30

Abstract: An encoder includes circuitry and memory coupled to the circuitry. In operation, for a group of layers including at least one output layer, the circuitry generates a bitstream including a common header for one or more layers in the group of layers, in which when a total number of layers in the group of layers is 1, (i) performance requirement information indicating a performance requirement for a decoder is signaled in the common header, and (ii) a hypothetical reference decoder (HRD) parameter is not signaled in the common header. The bitstream includes the common header and encoded data of at least one image in the at least one output layer. The common header does not include the HRD parameter.

公开(公告)号：US12143583B2

公开(公告)日：2024-11-12

申请号：US17071470

申请日：2020-10-15

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/12 ,  H04N19/126 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry: performs a transform process of (i) applying a first transform to a prediction residual signal indicating a difference between a current block to be encoded and a prediction image of the current block and (ii) further applying a second transform to a transform result of the first transform; and in the second transform, selects one transform basis (i) from a first group of candidates when a size of the current block is a first block size and (ii) from a second group of candidates when the size of the current block is a second block size different from the first block size, the first group including one or more candidates for a transform basis, the second group being different from the first group.

公开(公告)号：US12137236B2

公开(公告)日：2024-11-05

申请号：US18235960

申请日：2023-08-21

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Virginie Drugeon ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/189 ,  H04N19/105 ,  H04N19/132 ,  H04N19/159 ,  H04N19/182

Abstract: An encoder includes circuitry and memory. The circuitry, using the memory: derives a one-dimensional array of a plurality of reference samples for intra prediction; performs smoothing on the one-dimensional array of the plurality of reference samples which has been derived; and generates a prediction image using the plurality of reference samples. In deriving the one-dimensional array, the circuitry projects a value of at least one decoded pixel located on a first line onto a second line perpendicular to the first line, to derive at least one of the plurality of reference samples, and the smoothing is performed on the at least one decoded pixel projected onto the second line.

公开(公告)号：US12113988B2

公开(公告)日：2024-10-08

申请号：US18204494

申请日：2023-06-01

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hideyuki Ohgose ,  Kiyofumi Abe ,  Hiroshi Arakawa ,  Tatsuro Juri ,  Kazuhito Kimura

IPC: H04N19/176 ,  H04N19/103 ,  H04N19/146 ,  H04N19/436 ,  H04N19/50

CPC classification number: H04N19/176 ,  H04N19/103 ,  H04N19/146 ,  H04N19/436 ,  H04N19/50

Abstract: A video image decoding device receives, as the code string to be decoded, a first code string to be decoded including information based on an encoded residual coefficient and header information or a second code string to be decoded including a residual image obtained in encoding the code string to be decoded and header information. The video image decoding device, when the code string to be decoded that is received by the receiver is the first code string to be decoded, adds the residual decoded image and the predictive image to each other to generate and output a reconstructed image and, when the code string to be decoded received by the receiver is the second code string to be decoded, adds a residual image included in the second code string to be decoded and the predictive image to each other to generate and output a reconstructed image.