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1.发明公开公开(公告)号：US20240275202A1
公开(公告)日：2024-08-15
申请号：US18569626
申请日：2022-08-17
Inventor： YUTA NAGATOMI , MASAFUMI NAKAMURA , MASATOSHI NAKASE , HIROKI AKASHI , KINYA KATO
CPC classification number: H02J9/061 , H02J7/00714 , H02J7/34 , H02J2207/20
Abstract: A backup power supply system (1) includes a first terminal (T1), a second terminal (T2), a disconnect device (10), a current detector (20), a charge/discharge device (30), an auxiliary power supply (40), and a controller (50). The disconnect device (10) is connected between the first terminal (T1) configured to be connected to a main power supply (2) and the second terminal (T2) configured to be connected to a load (3). The charge/discharge device (30) is connected between the auxiliary power supply (40) and a node (P1) between the disconnect device (10) and the second terminal (T2). The charge/discharge device (30) is configured to receive power supplied from main power supply (2) to cause a charging current to flow to the auxiliary power supply (40) in a non-defective state in which the main power supply (2) is not defective. The charge/discharge device (30) is configured to receive power supplied from the auxiliary power supply (40) to cause a discharging current to flow to the load (3) in a defective state. The controller (50) is configured to have the disconnect device (10) be in a connecting state while the current detector (20) does not detect the discharging current, and to have the disconnect device (10) be in a disconnecting state while the current detector (20) detects the discharging current.
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2.发明公开公开(公告)号：US20240313765A1
公开(公告)日：2024-09-19
申请号：US18571215
申请日：2022-06-23
Inventor： HIROKI AKASHI , YOHSUKE MITANI , YUTA NAGATOMI , MASAFUMI NAKAMURA , MASATOSHI NAKASE , KINYA KATO , YASUHIRO IIJIMA
IPC: H03K17/30 , H03K17/06 , H03K17/081
CPC classification number: H03K17/302 , H03K17/063 , H03K17/08104 , H03K2217/0081
Abstract: In a backup power supply system according to the present invention, in a non-defective state in which a main power supply is not defective, a controller turns on a first field-effect transistor and causes a third field-effect transistor to operate in an active region so as to charge the power storage device from the main power supply via a charging path through the first field-effect transistor, the second field-effect transistor, and the third field-effect transistor. In a defective state in which the main power supply is defective, the controller turns off the first field-effect transistor and turns on the second field-effect transistor and the third field-effect transistor so as to supply power from the power storage device to the load.
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公开(公告)号：US20230024780A1
公开(公告)日：2023-01-26
申请号：US17758404
申请日：2020-12-17
Inventor： HIROKI AKASHI , TAKUYA ISHII , YOSHIHITO KAWAKAMI , KAZUHIRO YAHATA , TAKESHI AZUMA , YOSHIHISA MINAMI
Abstract: A switch circuit is configured of a first semiconductor element and a second semiconductor element connected in series, and receives a DC voltage of 100 V or more. The drive circuit causes the first semiconductor element or the second semiconductor element to perform a switching operation. The isolated power supply circuit converts a predetermined power supply voltage into an isolated first power supply voltage, and outputs the first power supply voltage to the drive circuit. The isolation signal converter converts a first signal of 6 MHz or more into an isolated first drive signal, and outputs the first drive signal to the drive circuit. The single substrate mounts the isolated power supply circuit and the isolation signal converter. Both the first semiconductor element and the second semiconductor element are wide bandgap semiconductor elements.
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公开(公告)号：US20230022728A1
公开(公告)日：2023-01-26
申请号：US17757973
申请日：2020-12-17
Inventor： TAKEYA OKUNO , MANABU YANAGIHARA , HIROKI AKASHI
Abstract: EMI noise is reduced and a component mounting area is suppressed, and downsizing of a power supply device is achieved. Power supply device includes transistor block, gate drive circuit block, and driver block. First gate terminal and second gate terminal are disposed on the same side as gate drive circuit block when viewed from a center of transistor block. Two output terminals are disposed on the same side as transistor block when viewed from a center of gate drive circuit block. At least a part of first drain terminal is included in a region sandwiched between first source terminal and second source terminal. Second drain terminal is disposed at a position deviating from an extension region that extends the region sandwiched between the first source terminal and the second source terminal beyond second source terminal as viewed from first drain terminal.
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