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1.
公开(公告)号:US20180007378A1
公开(公告)日:2018-01-04
申请号:US15684212
申请日:2017-08-23
Inventor: Kengo TERADA , Hisao SASAI , Satoshi YOSHIKAWA
IPC: H04N19/50 , H04N19/573 , H04N19/58 , H04N5/232
CPC classification number: H04N19/50 , H04N5/23229 , H04N19/573 , H04N19/58
Abstract: An image coding apparatus, including an encoder and a memory, and an image coding method are provided. In the image coding apparatus, the encoder executes operations, including obtaining a reference-specific image from storage accessible by the encoder, the reference-specific image being referenced from one or more other images to be displayed, and storing the reference-specific image in the memory. The operations further include encoding one or more to-be-displayed images by referring to the reference-specific image, wherein the obtained reference-specific image is formed by integrating a plurality of images. An image decoding apparatus and an image decoding method are also provided.
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公开(公告)号:US20220351092A1
公开(公告)日:2022-11-03
申请号:US17751932
申请日:2022-05-24
Inventor: Yoshinori OKAZAKI , Takashi YAMADA , Yoshito TANAKA , Hisao SASAI , Makoto KAWASAKI
Abstract: A space staging method includes a reservation information acquisition step, an entry detection step, a determination step, and a staging execution step. The reservation information acquisition step is a step of acquiring reservation information about a reservation of a target space of a facility from a server. The entry detection step is a step of detecting whether a user specified by the reservation information has entered a specific space in the facility. The determination step is a step of determining a number of times of entry of the user into the specific space upon detection of entry of the user into the specific space in the entry detection step. The staging execution step is a step of causing a staging system generating a stimulus to at least one of five senses of human in the facility to execute staging processing.
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3.
公开(公告)号:US20180041767A1
公开(公告)日:2018-02-08
申请号:US15785756
申请日:2017-10-17
Inventor: Satoshi YOSHIKAWA , Hisao SASAI , Kengo TERADA
IPC: H04N19/50 , H04N19/176 , H04N19/182 , H04N19/46
CPC classification number: H04N19/50 , H04N19/176 , H04N19/182 , H04N19/46
Abstract: An image decoding device is provided for decoding a current block in a current coded picture using a coded bitstream. The image decoding device includes a processor and a memory coupled to the processor. The processor of the image decoding device performs operations, including decoding first motion information for the current block from the coded bitstream, and selecting second motion information from a decoded region adjacent to the current block. The processor also performs operations including decoding the current block using the decoded first motion information and the decoded second motion information, and generating a decoded picture using the decoded current block.
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公开(公告)号:US20250047888A1
公开(公告)日:2025-02-06
申请号:US18924514
申请日:2024-10-23
Inventor: Satoshi YOSHIKAWA , Hisao SASAI , Kengo TERADA
IPC: H04N19/50 , H04N19/176 , H04N19/182 , H04N19/46
Abstract: A decoder, encoder, and a recording medium causes a processor to generate a prediction image by an inter prediction process by i) obtaining first information from a bitstream associated with a variable number of feature points of a current block usable in performing an affine prediction, ii) obtaining a flag from the bitstream indicating a first or second value, iii) obtaining second information from the bitstream specifying first points in response to the flag indicating the first value, iv) determining third information provided the first points based on the second information and indicating a difference between coordinate values of a first point and a corresponding second point included in a reference picture, v) generating a prediction image of the current block according to the determined third information, and vi) refraining from obtaining the second information from the bitstream, in response to the flag indicating the second value.
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公开(公告)号:US20220116641A1
公开(公告)日:2022-04-14
申请号:US17558755
申请日:2021-12-22
Inventor: Satoshi YOSHIKAWA , Hisao SASAI , Kengo TERADA
IPC: H04N19/50
Abstract: A decoder includes a memory and a processor coupled to the memory. The processor is configured to obtain first information from a bitstream, the first information indicating a number of first points in a current picture. The processor is also configured to determine second information provided for each of the first points based on the first information, the second information indicating a difference between a coordinate value of a first point and a coordinate value of a corresponding second point, the corresponding second point being included in a reference picture. The processor is further configured to generate a prediction image of a current block by performing an affine prediction according to the determined second information.
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