公开(公告)号：US06704697B1

公开(公告)日：2004-03-09

申请号：US09443685

申请日：1999-11-18

申请人： Paul Berevoescu ,  Oleg Levitsky

发明人： Paul Berevoescu ,  Oleg Levitsky

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A modeling method to improve the accuracy of timing analysis that more closely models timing information associated with layout parasitics that are connected to interface pins of a transistor-level subcircuit. A method is described for performing a hierarchical timing analysis of a circuit having a transistor-level subcircuit. Certain data (e.g., the layout parasitic data associated with interface nodes) associated with the transistor-level subcircuit are set aside. A timing model (timing arcs) of the transistor-level subcircuit is created without using these data. The timing analysis of the circuit is performed using a circuit analyzer. The circuit analyzer uses the timing model (timing arcs) and the layout parasitic data for the transistor-level subcircuit in the timing analysis. Thus, the layout parasitic data associated with the lower level subcircuit is preserved and used in the higher level circuit timing analysis to provide an accurate non-linear timing analysis of the layout parasitics.

摘要翻译： 一种提高定时分析准确度的建模方法，可以更精确地模拟与连接到晶体管级子电路的接口引脚的布局寄生相关联的定时信息。 描述了一种用于执行具有晶体管级子电路的电路的分层定时分析的方法。 与晶体管级子电路相关联的某些数据（例如，与接口节点相关联的布局寄生数据）被放在一边。 创建晶体管级子电路的定时模型（定时弧），而不使用这些数据。 使用电路分析仪进行电路的时序分析。 电路分析仪在时序分析中使用时序模型（定时弧）和晶体管级子电路的布局寄生数据。 因此，与较低级子电路相关联的布局寄生数据被保留并用于较高级别的电路定时分析中，以提供布局寄生效应的精确非线性时序分析。

公开(公告)号：US06378113B1

公开(公告)日：2002-04-23

申请号：US09428603

申请日：1999-10-27

申请人： Oleg Levitsky ,  Paul Berevoescu

发明人： Oleg Levitsky ,  Paul Berevoescu

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： A modeling method to incorporate transparency into black box models using setup time in a circuit timing model. The circuit timing model, comprising a plurality of latches initially represented using black box models, is generated. For each of the plurality of latches, an arrival time is calculated from the latch clock pin to an interface data output pin of the timing model, and the maximum arrival time is determined. For each of the plurality of latches, a setup time is calculated. A setup time is also calculated using the delay time from the interface data input pin to the interface data output pin and the maximum arrival time. The worst-case set up time is selected from these setup times and imposed at the interface data input pin. Satisfaction of the worst-case setup time causes the maximum arrival time to also be satisfied. Therefore, a transparent path through the latches in a black box timing model cannot generate an arrival time at the interface data output pin greater than the maximum permissible arrival time. Thus, the timing constraints used in the black box timing model are not unnecessarily restrictive.

摘要翻译： 一种使用电路时序模型中的建立时间将透明度并入黑盒子模型的建模方法。 生成包括使用黑箱模型初始表示的多个锁存器的电路定时模型。 对于多个锁存器中的每一个，从锁存时钟引脚到定时模型的接口数据输出引脚计算到达时间，并且确定最大到达时间。 对于多个锁存器中的每一个，计算建立时间。 还可以使用从接口数据输入引脚到接口数据输出引脚的延迟时间和最大到达时间来计算设置时间。 从这些设置时间选择最坏情况下的设置时间，并在接口数据输入引脚处施加。 对最坏情况设置时间的满意度也使得最大到达时间也得到满足。 因此，通过黑盒定时模型中的锁存器的透明路径不能在接口数据输出端产生大于最大允许到达时间的到达时间。 因此，黑盒定时模型中使用的时序约束不是不必要的限制。