公开(公告)号：US06704697B1

公开(公告)日：2004-03-09

申请号：US09443685

申请日：1999-11-18

申请人： Paul Berevoescu ,  Oleg Levitsky

发明人： Paul Berevoescu ,  Oleg Levitsky

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A modeling method to improve the accuracy of timing analysis that more closely models timing information associated with layout parasitics that are connected to interface pins of a transistor-level subcircuit. A method is described for performing a hierarchical timing analysis of a circuit having a transistor-level subcircuit. Certain data (e.g., the layout parasitic data associated with interface nodes) associated with the transistor-level subcircuit are set aside. A timing model (timing arcs) of the transistor-level subcircuit is created without using these data. The timing analysis of the circuit is performed using a circuit analyzer. The circuit analyzer uses the timing model (timing arcs) and the layout parasitic data for the transistor-level subcircuit in the timing analysis. Thus, the layout parasitic data associated with the lower level subcircuit is preserved and used in the higher level circuit timing analysis to provide an accurate non-linear timing analysis of the layout parasitics.

摘要翻译： 一种提高定时分析准确度的建模方法，可以更精确地模拟与连接到晶体管级子电路的接口引脚的布局寄生相关联的定时信息。 描述了一种用于执行具有晶体管级子电路的电路的分层定时分析的方法。 与晶体管级子电路相关联的某些数据（例如，与接口节点相关联的布局寄生数据）被放在一边。 创建晶体管级子电路的定时模型（定时弧），而不使用这些数据。 使用电路分析仪进行电路的时序分析。 电路分析仪在时序分析中使用时序模型（定时弧）和晶体管级子电路的布局寄生数据。 因此，与较低级子电路相关联的布局寄生数据被保留并用于较高级别的电路定时分析中，以提供布局寄生效应的精确非线性时序分析。

公开(公告)号：US06378113B1

公开(公告)日：2002-04-23

申请号：US09428603

申请日：1999-10-27

申请人： Oleg Levitsky ,  Paul Berevoescu

发明人： Oleg Levitsky ,  Paul Berevoescu

IPC分类号： G06F1750

CPC分类号： G06F17/5031

摘要： A modeling method to incorporate transparency into black box models using setup time in a circuit timing model. The circuit timing model, comprising a plurality of latches initially represented using black box models, is generated. For each of the plurality of latches, an arrival time is calculated from the latch clock pin to an interface data output pin of the timing model, and the maximum arrival time is determined. For each of the plurality of latches, a setup time is calculated. A setup time is also calculated using the delay time from the interface data input pin to the interface data output pin and the maximum arrival time. The worst-case set up time is selected from these setup times and imposed at the interface data input pin. Satisfaction of the worst-case setup time causes the maximum arrival time to also be satisfied. Therefore, a transparent path through the latches in a black box timing model cannot generate an arrival time at the interface data output pin greater than the maximum permissible arrival time. Thus, the timing constraints used in the black box timing model are not unnecessarily restrictive.

摘要翻译： 一种使用电路时序模型中的建立时间将透明度并入黑盒子模型的建模方法。 生成包括使用黑箱模型初始表示的多个锁存器的电路定时模型。 对于多个锁存器中的每一个，从锁存时钟引脚到定时模型的接口数据输出引脚计算到达时间，并且确定最大到达时间。 对于多个锁存器中的每一个，计算建立时间。 还可以使用从接口数据输入引脚到接口数据输出引脚的延迟时间和最大到达时间来计算设置时间。 从这些设置时间选择最坏情况下的设置时间，并在接口数据输入引脚处施加。 对最坏情况设置时间的满意度也使得最大到达时间也得到满足。 因此，通过黑盒定时模型中的锁存器的透明路径不能在接口数据输出端产生大于最大允许到达时间的到达时间。 因此，黑盒定时模型中使用的时序约束不是不必要的限制。

公开(公告)号：US09141740B2

公开(公告)日：2015-09-22

申请号：US13077933

申请日：2011-03-31

申请人： Dongzi Liu ,  Oleg Levitsky

发明人： Dongzi Liu ,  Oleg Levitsky

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F17/5068 ,  G06F2217/84

摘要： Disclosed are methods, systems, and articles of manufacture for implementing full-chip optimization across block boundaries with reduced physical design data. Some embodiments create a partial netlist and reduced physical data by identifying and including side instance(s) or side path(s) in the reduced physical data and then include or exclude side instance(s) or side path(s) in the reduced physical data. The method or the system may then perform full-chip optimization across individual block boundaries with the reduced physical data. Some embodiments further merge the post-optimization data back into the original data while reducing logic and physical disturbance to existing designs. Some embodiments anchor driver instance(s) that correspond to excluded side instance(s) or side path(s) to ensure LEC cleanliness and may further trim timing graph(s) based at least on the partial netlist. Some embodiments account for parasitics without static parasitic files. Various embodiments apply to both hierarchical and non-hierarchical designs.

摘要翻译： 公开了用于通过减少的物理设计数据实现跨块边界的全芯片优化的方法，系统和制品。 一些实施例通过识别并包括减少的物理数据中的侧边实例或侧路径来创建部分网表和减少的物理数据，然后包括或排除减少的物理中的侧边或侧边路径 数据。 该方法或系统然后可以通过减少的物理数据在单独的块边界上执行全片优化。 一些实施例进一步将后优化数据合并回原始数据，同时减少对现有设计的逻辑和物理干扰。 一些实施例对应于排除的侧面实例或侧路径的锚点驱动器实例以确保LEC清洁度并且可以至少基于部分网表进一步修整定时图。 一些实施例解释了没有静态寄生文件的寄生效应。 各种实施例适用于分层和非分层设计。

公开(公告)号：US08935642B1

公开(公告)日：2015-01-13

申请号：US13716127

申请日：2012-12-15

申请人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

发明人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

摘要翻译： 在本发明的一个实施例中，一种方法包括将集成电路设计划分成顶层和多个分区的层级，其中顶层包括顶级网表，每个分区包括分区网表; 接收所述集成电路设计的所述多个分区中的每一个的数据路径定时预算和时钟路径时序预算; 以及响应于相应的数据路径定时预算和时钟路径定时预算，生成每个分区的定时预算模型，其中每个定时预算模型包括用于每个相应分区的分区内时钟定时约束，用于独立实现顶层。

公开(公告)号：US08151229B1

公开(公告)日：2012-04-03

申请号：US11733749

申请日：2007-04-10

申请人： Hongliang Chang ,  Oleg Levitsky ,  Nikolay Rubanov ,  Vassilios Gerousis

发明人： Hongliang Chang ,  Oleg Levitsky ,  Nikolay Rubanov ,  Vassilios Gerousis

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A system and method for determining the criticality of each timing pin in a circuit design are disclosed. The criticality of a timing pin is the probability that the timing pin is on the path with the worst slack in the circuit design. According to the methodology, the slack for each timing pin is calculated, wherein each slack is a function of a process random variable. Then, the criticality of each timing pin is determined as the probability of the timing pin having the minimum slack among the slacks in an independent critical set of timing pins. The criticality of each timing pin may then be normalized. By determining the criticalities of the timing pins in a circuit design, a circuit design system may be able to more easily identify portions of the circuit design that need modification for timing and other purposes.

摘要翻译： 公开了一种用于确定电路设计中每个定时引脚的关键性的系统和方法。 定时引脚的关键是定时引脚在电路设计中最差松弛的路径上的可能性。 根据该方法，计算每个定时针的松弛，其中每个松弛是过程随机变量的函数。 然后，每个定时引脚的临界值被确定为定时引脚在独立关键的定时引脚组中的松弛中具有最小松弛的概率。 然后可以对每个定时引脚的临界值进行归一化。 通过确定电路设计中的定时引脚的关键性，电路设计系统可能能够更容易地识别电路设计中需要针对时序和其他目的进行修改的部分。

公开(公告)号：US08977994B1

公开(公告)日：2015-03-10

申请号：US12983247

申请日：2010-12-31

申请人： Oleg Levitsky ,  Chien-Chu Kuo ,  Dinesh Gupta

发明人： Oleg Levitsky ,  Chien-Chu Kuo ,  Dinesh Gupta

IPC分类号： G06F17/50

CPC分类号： G06F17/5031 ,  G06F17/505 ,  G06F2217/84

摘要： A system and method of designing an integrated circuit capable of deriving timing constraints for individual block-level circuits of an integrated circuit that are derived from the chip-level timing constraints and analysis. The block-level timing constraints are in the form of one or more logical timing constraint points at the input and output ports of block-level circuits. Each logical timing constraint points specifies a clock source used to clock data through the port, a delay parameter specifying data propagation delay backward from an input port and forward from an output port, and any timing exception associated with the data path. Using the logical timing constraint point, the circuit design system performs independent timing analysis and optimization of each block-level circuit. The system then reassembles the block-level circuits into a modified chip-level circuit for which timing closure can be achieved.

摘要翻译： 一种设计集成电路的系统和方法，该集成电路能够导出从芯片级定时约束和分析导出的集成电路的各个块级电路的时序约束。 块级定时约束是块级电路的输入和输出端口处的一个或多个逻辑时序约束点的形式。 每个逻辑时序约束点指定用于通过端口对数据进行时钟源的时钟源，从输入端口向后指定数据传播延迟并从输出端口转发的延迟参数以及与数据路径相关联的任何定时异常。 使用逻辑时序约束点，电路设计系统对每个块级电路进行独立的时序分析和优化。 然后，系统将块级电路重新组装成可以实现时序闭合的修改的芯片级电路。

公开(公告)号：US08640066B1

公开(公告)日：2014-01-28

申请号：US12897777

申请日：2010-10-04

申请人： Dinesh Gupta ,  Oleg Levitsky

发明人： Dinesh Gupta ,  Oleg Levitsky

IPC分类号： G06F17/50

CPC分类号： G06F17/50 ,  G06F17/505 ,  G06F2217/84

摘要： In one embodiment, a method of designing an integrated circuit is disclosed, including receiving a first partition block for a top level of a hierarchical design of an integrated circuit; analyzing each pin of the first partition block for an attribute associated with the pin indicating a timing exception; and if a timing exception other than false path is indicated then generating an internal timing pin in a first timing graph model of the first partition block for each timing exception, and adding a timing arc and a dummy arc coupled to the internal timing pin in the first timing graph model of the first partition block. The internal timing pin adds a timing exception constraint for each timing exception. Timing of the top level may then be analyzed with the first timing graph model to determine if timing constraints, including the added timing exception constraints, are met.

摘要翻译： 在一个实施例中，公开了一种设计集成电路的方法，包括接收用于集成电路的分层设计的顶层的第一分区块; 分析第一分区块的每个引脚以获得与引脚相关联的指示定时异常的属性; 并且如果指示除了假路径之外的定时异常，则针对每个定时异常在第一分区块的第一定时图模型中生成内部定时引脚，并且将定时弧和虚拟电弧相加到内部定时引脚 第一分区块的第一时序图模型。 内部定时引脚为每个定时异常添加时序异常约束。 然后可以用第一时序图模型来分析顶级的定时，以确定是否满足包括添加的时序异常约束的时序约束。

公开(公告)号：US08572532B1

公开(公告)日：2013-10-29

申请号：US13487157

申请日：2012-06-01

申请人： Sushobhit Singh ,  Amit Kumar ,  Oleg Levitsky ,  Akash Khandelwal

发明人： Sushobhit Singh ,  Amit Kumar ,  Oleg Levitsky ,  Akash Khandelwal

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： A method of timing analysis of an integrated circuit (IC) design with a partition block including an original clock signal with a pair of clock paths having an external common point outside the block boundary is disclosed, including receiving a netlist of the partition block of a hierarchical IC design, analyzing a pair of clock paths having the external common point to determine first and second clock ports at the boundary of the partition block; and for the first and second clock ports, creating launch and capture clocks, making exclusive clock groups of the launch clock and the capture clock for opposing clock ports to avoid the launch and capture clocks for each port affecting other internal data paths within the partition block, and associating common path pessimism removal information with a source latency of the capture clock to adjust timing at an end point of the internal data path.

摘要翻译： 公开了一种具有包括具有在块边界外部具有外部公共点的一对时钟路径的原始时钟信号的分区块的集成电路（IC）设计的定时分析的方法，包括：接收一个 分析IC设计，分析具有外部公共点的一对时钟路径，以确定分区块边界处的第一和第二时钟端口; 并为第一个和第二个时钟端口创建启动和捕获时钟，制作发射时钟的专用时钟组和相应时钟端口的捕获时钟，以避免每个端口的启动和捕获时钟影响分区块内的其他内部数据路径 并且将公共路径悲观消除信息与捕获时钟的源延迟相关联，以调整内部数据路径的终点处的定时。

公开(公告)号：US08539402B1

公开(公告)日：2013-09-17

申请号：US13716129

申请日：2012-12-15

申请人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

发明人： Vivek Bhardwaj ,  Oleg Levitsky ,  Dinesh Gupta

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5031 ,  G06F17/505 ,  G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： In one embodiment of the invention, a method includes partitioning an integrated circuit design into a hierarchy of a top level and a plurality of partitions, wherein the top level includes a top level netlist and each partition includes a partition netlist; receiving data path timing budgets and clock path timing budgets for each of the plurality of partitions of the integrated circuit design; and generating a timing budget model of each partition in response to the respective data path timing budgets and clock path timing budgets, wherein each timing budget model includes an intra-partition clock timing constraint for each respective partition for independent implementation of the top level.

摘要翻译： 在本发明的一个实施例中，一种方法包括将集成电路设计划分成顶层和多个分区的层级，其中顶层包括顶级网表，每个分区包括分区网表; 接收所述集成电路设计的所述多个分区中的每一个的数据路径定时预算和时钟路径时序预算; 以及响应于相应的数据路径定时预算和时钟路径定时预算，生成每个分区的定时预算模型，其中每个定时预算模型包括用于每个相应分区的分区内时钟定时约束，用于独立实现顶层。

公开(公告)号：US08745560B1

公开(公告)日：2014-06-03

申请号：US13767871

申请日：2013-02-14

申请人： Vivek Bhardwaj ,  Didier Seropian ,  Oleg Levitsky

发明人： Vivek Bhardwaj ,  Didier Seropian ,  Oleg Levitsky

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/5036 ,  G06F2217/84

摘要： In one embodiment of the invention, a method includes reading an automatically generated timing budgeting file, including timing budget information for a plurality of partitions of an integrated circuit design; graphically displaying a time budgeting debug window on a display device; and graphically displaying a timing budget analyzer window on the display device in response to selection of a selected signal path in a path list window pane. The timing budget analyzer window graphically displays timing budgets and timing delays of a selected path for visual comparison. The time budgeting debug window includes a button with a path category menu to display one or more signal paths meeting a selected path category, and a path list window pane to display a list of one or more signal paths through one or more ports of the plurality of partitions in response to the selected path category in the path category menu.

摘要翻译： 在本发明的一个实施例中，一种方法包括读取自动生成的定时预算文件，包括集成电路设计的多个分区的定时预算信息; 在显示设备上以图形方式显示时间预算调试窗口; 以及响应于在路径列表窗格中选择所选择的信号路径，在显示设备上图形地显示定时预算分析器窗口。 时间预算分析器窗口以图形方式显示所选路径的时序预算和定时延迟，用于视觉比较。 时间预算调试窗口包括具有路径类别菜单的按钮，用于显示满足所选路径类别的一个或多个信号路径，以及路径列表窗格窗格，用于显示通过多个端口中的一个或多个端口的一个或多个信号路径的列表 的分区响应于路径类别菜单中选择的路径类别。