公开(公告)号：US5889975A

公开(公告)日：1999-03-30

申请号：US746285

申请日：1996-11-07

申请人： Paul G. Meyer ,  Stephen Strazdus ,  Dennis O'Connor ,  Thomas Adelmeyer ,  Jay Heeb ,  Avery Topps

发明人： Paul G. Meyer ,  Stephen Strazdus ,  Dennis O'Connor ,  Thomas Adelmeyer ,  Jay Heeb ,  Avery Topps

IPC分类号： G06F9/38

CPC分类号： G06F9/3802 ,  G06F9/3867

摘要： A processor core suitable for use with a wide variety of instruction fetch units. The processor core contains a plurality of pipe stages including an instruction pointer generation stage and a decode stage. The core bundles all control necessary for downstream pipeline operation with an instruction address in a first stage. The bundle is transmitted outside the core to the instruction fetch unit. The instruction fetch unit fetches the instruction and adds it to the bundle, before forwarding the bundle as modified back within the core and down the pipeline. In this way, an external pipe stage is introduced providing a connection between discontinuous pipe stages in the core. Additionally, by bundling the control signals and address information in a single bundle that traverses the external pipe stage as a group, synchronization concerns are reduced or eliminated.

摘要翻译： 适用于各种指令提取单元的处理器核心。 处理器核心包括多个管级，包括指令指针生成级和解码级。 核心将下游管道运行所需的所有控制与第一阶段的指令地址进行捆绑。 捆绑包在核心外部传送到指令提取单元。 指令提取单元获取指令并将其添加到捆绑包中，然后在内核中转发捆绑包，然后在管道中进行修改。 以这种方式，引入外部管段，提供芯中不连续管段之间的连接。 此外，通过将跨越外部管道级的单个束中的控制信号和地址信息捆绑为一组，减少或消除了同步问题。

公开(公告)号：US5423016A

公开(公告)日：1995-06-06

申请号：US840464

申请日：1992-02-24

申请人： Kenichi Tsuchiya ,  Lewis A. Boone ,  Michael L. Haupt ,  Thomas Adelmeyer

发明人： Kenichi Tsuchiya ,  Lewis A. Boone ,  Michael L. Haupt ,  Thomas Adelmeyer

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0888 ,  G06F12/0859

摘要： A method of and apparatus for efficiently transferring data between a memory system and an instruction processor having a dedicated cache memory. A read request within the instruction processor for a data element not currently stored within the dedicated cache memory creates a read cache miss condition. A transfer of the eight word block containing the requested data element is initiated from the memory system beginning with the 72 bit double word containing the requested data element. The eight word block of data is placed into a block buffer upon being received by the instruction processor. The instruction processor is permitted to resume instruction execution and access to the cache memory as soon as the requested data element has been received by the block buffer. The eight word data block is transferred from the block buffer to cache memory at the next read cache miss condition. The block buffer has a no save designator for block transfers and other accesses for which near term subsequent access to buffered data is unlikely. Data designated no save is not transferred from the block buffer to the cache memory.

摘要翻译： 一种用于在存储器系统和具有专用高速缓冲存储器的指令处理器之间有效地传送数据的方法和装置。 在指令处理器内对于当前未存储在专用高速缓冲存储器中的数据元素的读请求产生读高速缓存未命中状态。 从包含请求的数据元素的72位双字开始的存储器系统中启动包含所请求的数据元素的八个字块的传送。 当指令处理器接收到8字数据块时，它被放入块缓冲器中。 一旦所请求的数据元素被块缓冲器接收，就允许指令处理器恢复指令执行并访问高速缓冲存储器。 在下一个读高速缓存未命中状态下，八字数据块从块缓冲器传送到高速缓冲存储器。 块缓冲区具有用于块传输和其他访问的无保存指示符，其中近期对缓冲数据的后续访问是不可能的。 数据指定为无保存不会从块缓冲区传输到高速缓存。