公开(公告)号：US08261360B2

公开(公告)日：2012-09-04

申请号：US11059419

申请日：2005-02-17

申请人： Miki Murakami ,  Kenichi Tsuchiya

发明人： Miki Murakami ,  Kenichi Tsuchiya

IPC分类号： G06F7/04 ,  G06F21/00

CPC分类号： H04L9/16 ,  H04L9/0822 ,  H04L2209/603

摘要： A content distributing system for distributing content disclosed herein is an encrypting apparatus for encrypting each of objects constituting content using a different encryption key, a content offering apparatus for offering the encrypted content to a content reproducing apparatus; a license information offering apparatus for offering license information including information necessary for decrypting the encrypted content, and a content reproducing apparatus for acquiring the encrypted content from the content offering apparatus in order to decrypt and reproduce the acquired content using the license information acquired from the license offering apparatus.

摘要翻译： 用于分发本文公开的内容的内容分发系统是用于使用不同的加密密钥加密构成内容的每个对象的加密装置，用于将内容提供装置提供给内容再现装置的加密内容; 许可证信息提供装置，用于提供包括解密加密内容所需的信息的许可信息;以及内容再现装置，用于从内容提供装置获取加密的内容，以便使用从许可证获取的许可证信息来解密和再现所获取的内容 提供仪器。

公开(公告)号：US20120066483A1

公开(公告)日：2012-03-15

申请号：US12882434

申请日：2010-09-15

申请人： Bechara F. Boury ,  Michael Bryan Mitchell ,  Paul Michael Steinmetz ,  Kenichi Tsuchiya

发明人： Bechara F. Boury ,  Michael Bryan Mitchell ,  Paul Michael Steinmetz ,  Kenichi Tsuchiya

IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F12/0875 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/3889

摘要： A computing device includes: an instruction cache storing primary execution unit instructions and auxiliary execution unit instructions in a sequential order; a primary execution unit configured to receive and execute the primary execution unit instructions from the instruction cache; an auxiliary execution unit configured to receive and execute only the auxiliary execution unit instructions from the instruction cache in a manner independent from and asynchronous to the primary execution unit; and completion circuitry configured to coordinate completion of the primary execution unit instructions by the primary execution unit and the auxiliary execution unit instructions according to the sequential order.

摘要翻译： 计算设备包括：指令高速缓存，以顺序的顺序存储主执行单元指令和辅助执行单元指令; 主执行单元，被配置为从指令高速缓存接收和执行主执行单元指令; 辅助执行单元，被配置为以与主执行单元无关并且与异步的方式从指令高速缓存接收并执行辅助执行单元指令; 以及完成电路，其被配置为根据顺序顺序来协调主执行单元和辅助执行单元指令执行主执行单元指令的完成。

公开(公告)号：US20110153955A1

公开(公告)日：2011-06-23

申请号：US12641766

申请日：2009-12-18

申请人： Benjamin Herrenschmidt ,  Jason M. Hopp ,  Kenichi Tsuchiya ,  Maciej P. Tyrlik

发明人： Benjamin Herrenschmidt ,  Jason M. Hopp ,  Kenichi Tsuchiya ,  Maciej P. Tyrlik

IPC分类号： G06F12/10 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/1018 ,  G06F12/1027 ,  G06F2212/652

摘要： A computer implemented method searches a unified translation lookaside buffer. Responsive to a request to access the unified translation lookaside buffer, a first order code within a first entry of a search priority configuration register is identified. A unified translation lookaside buffer is then searched according to the first order code for a hashed page entry. If the hashed page entry is not found when searching a unified translation lookaside buffer according to the first order code, a second order code is identified within a second entry of the search priority configuration register. The unified translation lookaside buffer is then searched according to the second order code for the hashed page entry.

摘要翻译： 计算机实现的方法搜索统一的翻译后备缓冲器。 响应于访问统一翻译后备缓冲器的请求，识别搜索优先级配置寄存器的第一条目内的第一订单代码。 然后根据散列页面条目的第一个订单代码搜索统一的翻译后备缓冲区。 如果在根据第一订单代码搜索统一的翻译后备缓冲器时找不到散列页条目，则在搜索优先级配置寄存器的第二条目内识别第二订单代码。 然后根据散列页面条目的二阶代码搜索统一的翻译后备缓冲区。

公开(公告)号：US07937568B2

公开(公告)日：2011-05-03

申请号：US11776121

申请日：2007-07-11

申请人： Anthony Correale, Jr. ,  Kenichi Tsuchiya

发明人： Anthony Correale, Jr. ,  Kenichi Tsuchiya

IPC分类号： G06F9/30 ,  G06F9/302

CPC分类号： G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/3836 ,  G06F9/3869 ,  Y02D10/126

摘要： A method, system and processor for increasing the instruction throughput in a processor executing longer latency instructions within the instruction pipeline. Logic associated with specific stages of the execution pipeline, responsible for executing the particular type of instructions, determines when at least a threshold number of the particular-type instructions is scheduled to be executed. The logic then automatically changes an execution cycle frequency of the specific pipeline stages from a first cycle frequency to a second, pre-established higher cycle frequency, which enables more efficient execution and higher execution throughput of the particular-type instructions. The cycle frequency of only the one or more functional stages are switched to the higher cycle frequency independent of the cycle frequency of the other functional stages in the processor pipeline. The logic also automatically switches the execution cycle frequency of the specific pipeline stages back from the second, higher cycle frequency to the first cycle frequency, when the number of scheduled first-type instructions has completed execution.

摘要翻译： 一种用于增加处理器中的指令吞吐量的方法，系统和处理器，其执行指令流水线内的较长延迟指令。 与执行流水线的特定阶段相关联的逻辑负责执行特定类型的指令，确定何时调度执行特定类型指令的至少一个阈值数目。 逻辑然后自动地将特定流水线级的执行周期频率​​从第一周期频率改变到第二预先建立的较高周期频率，这使得能够更有效地执行特定类型指令的执行吞吐量。 只有一个或多个功能级的周期频率被切换到与处理器管线中的其他功能级的周期频率无关的较高周期频率。 当调度的第一类型指令的数量已经完成执行时，逻辑还自动将特定流水线级的执行周期频率​​从第二较高周期频率切换到第一周期频率。

公开(公告)号：US20090019265A1

公开(公告)日：2009-01-15

申请号：US11776222

申请日：2007-07-11

申请人： ANTHONY CORREALE, JR. ,  Kenichi Tsuchiya

发明人： ANTHONY CORREALE, JR. ,  Kenichi Tsuchiya

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3296 ,  G06F9/30145 ,  G06F9/3869 ,  Y02D10/126 ,  Y02D10/172

摘要： A method, system and processor for adaptively and selectively controlling the instruction execution frequency of a data processor. Processing logic or a software compiler determines when a number of first-type instructions, requiring longer execution latency, are scheduled to be executed. The logic/compiler then triggers the CPM unit to automatically switch the execution frequency of the instruction processor from a first frequency that is optimal for processing regular-type instructions to a second, pre-established lower frequency that is optimal for processing the first-type instructions, to enable more efficient execution and higher execution throughput of the number of first-type operations within the processor. When the first-type instructions have completed execution, the processor's instruction execution frequency is returned to the first optimal frequency.

摘要翻译： 一种用于自适应地和选择性地控制数据处理器的指令执行频率的方法，系统和处理器。 处理逻辑或软件编译器确定何时调度执行需要更长执行延迟的第一类指令。 逻辑/编译器然后触发CPM单元自动地将指令处理器的执行频率从处理规则类型指令的最佳的第一频率切换到对于处理第一类型的处理最佳的第二预先建立的较低频率 指令，以实现处理器内第一类型操作数量的更高效的执行和更高的执行吞吐量。 当第一类指令完成执行时，处理器的指令执行频率返回到第一最佳频率。

公开(公告)号：US20080320236A1

公开(公告)日：2008-12-25

申请号：US11767882

申请日：2007-06-25

申请人： Makoto Ueda ,  Kenichi Tsuchiya ,  Takeo Nakada ,  Norio Fujita

发明人： Makoto Ueda ,  Kenichi Tsuchiya ,  Takeo Nakada ,  Norio Fujita

IPC分类号： G06F12/08

CPC分类号： G06F12/0831 ,  G06F12/0811 ,  G06F12/0813

摘要： A system includes processor units, caches, memory shared by the processor units, a system bus interface, and a cache snoop interfaces. Each processor unit has one of the caches. The system bus interface communicatively connects the processor units to the memory via at least the caches, and is a non-cache snoop system bus interface. The cache snoop interface communicatively connects the caches, and is independent of the system bus interface. Upon a given processor unit writing a new value to an address within the memory such that the new value and the address are cached within the cache of the given processor unit a write invalidation event is sent over the cache snoop interface to the caches of the processor units other than the given processor unit. This event invalidates the address as stored within any of the caches other than the cache of the given processor unit.

摘要翻译： 系统包括处理器单元，高速缓存，由处理器单元共享的存储器，系统总线接口和高速缓存监听接口。 每个处理器单元都有一个高速缓存。 系统总线接口至少通过高速缓存通信地将处理器单元连接到存储器，并且是非高速缓存监听系统总线接口。 缓存监听接口通信地连接高速缓存，并且独立于系统总线接口。 在给定处理器单元向存储器中的地址写入新值使得新值和地址被缓存在给定处理器单元的高速缓存内时，写无效事件通过高速缓存侦听接口发送到处理器的高速缓存 单位除了给定的处理器单位。 该事件将存储在除了给定处理器单元的高速缓存之外的任何高速缓存中的地址无效。

公开(公告)号：US20080022044A1

公开(公告)日：2008-01-24

申请号：US11835519

申请日：2007-08-08

申请人： Nathan Nunamaker ,  Jack Randolph ,  Kenichi Tsuchiya

发明人： Nathan Nunamaker ,  Jack Randolph ,  Kenichi Tsuchiya

IPC分类号： G06F12/00

CPC分类号： G06F9/30138 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3851 ,  G06F9/3861 ,  G06F12/0875

摘要： A processor contains multiple levels of registers having different access latency. A relatively smaller set of registers is contained in a relatively faster higher level register bank, and a larger, more complete set of the registers is contained in a relatively slower lower level register bank. Physically, the higher level register bank is placed closer to functional logic which receives inputs from the registers. Selection logic enables selecting output of either register bank for input to processor execution logic. Preferably, the lower level bank includes a complete set of all processor registers, and the higher level bank includes a smaller subset of the registers, duplicating information in the lower level bank. The higher level bank is preferably accessible in a single clock cycle.

摘要翻译： 处理器包含具有不同访问延迟的多级寄存器。 相对较小的寄存器集合包含在相对较快的较高级别的寄存器组中，并且较大的更完整的寄存器集合包含在相对较慢的较低级别的寄存器组中。 在物理上，较高级别的寄存器组被放置得更接近从寄存器接收输入的功能逻辑。 选择逻辑使能选择任一寄存器组的输出，以输入到处理器执行逻辑。 优选地，下级存储体包括一整套所有处理器寄存器，并且较高级存储体包括较小的寄存器子集，复制下级存储体中的信息。 较高级别的存储体优选在单个时钟周期内可访问。

公开(公告)号：US20060236080A1

公开(公告)日：2006-10-19

申请号：US11109001

申请日：2005-04-19

申请人： Richard Doing ,  Brett Olsson ,  Kenichi Tsuchiya

发明人： Richard Doing ,  Brett Olsson ,  Kenichi Tsuchiya

IPC分类号： G06F15/00

CPC分类号： G06F9/3804 ,  G06F9/3844

摘要： A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.

摘要翻译： 一种用于减少预测的分支指令的目标指令的获取时间的方法和处理器。 缓冲器中的每个条目（这里称为“分支目标缓冲器”）可以存储预测的分支指令的地址和从预测的分支指令的目标地址开始的指令。 当从指令高速缓存中取出指令时，使用获取的指令的特定位来对分支目标缓冲器中的特定条目进行索引。 将索引条目中的分支指令的地址与从指令高速缓存获取的指令的地址进行比较。 如果有匹配，则从该分支指令的目标地址开始的指令直接在分支指令的后面进行调度。 以这种方式，减少预测的分支指令的目标指令的获取时间。

公开(公告)号：US20060036811A1

公开(公告)日：2006-02-16

申请号：US10915982

申请日：2004-08-11

申请人： James Dieffenderfer ,  Richard Doing ,  Brian Frankel ,  Kenichi Tsuchiya

发明人： James Dieffenderfer ,  Richard Doing ,  Brian Frankel ,  Kenichi Tsuchiya

IPC分类号： G06F12/00

CPC分类号： G06F12/126 ,  G06F12/125

摘要： An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.

摘要翻译： 用于跟踪关联高速缓存行的访问的LRU数组和方法。 缓存中最近访问的行在表中标识，并且可以阻止缓存行被替换。 LRU阵列包含具有代表相关高速缓存的每行的数据行的数据阵列，其具有公共地址部分。 高速缓存行的第一组数据相对于每隔一个方式识别每个方式的高速缓存行的相对年龄。 第二组数据识别一条路线是否不被替换。 对于高速缓存行替换，高速缓存控制器将使用LRU阵列的内容来选择最近访问的行，考虑第一组数据的值，以及第二组数据的值，指示一种方式是否为 锁定 对LRU的更新发生在每个预取或提取行之后，或者替换高速缓存中的另一行时。

公开(公告)号：US06918866B2

公开(公告)日：2005-07-19

申请号：US10633910

申请日：2003-08-04

申请人： Shiro Miyamori ,  Yasuyuki Hayasaki ,  Masanari Umeda ,  Kenichi Tsuchiya

发明人： Shiro Miyamori ,  Yasuyuki Hayasaki ,  Masanari Umeda ,  Kenichi Tsuchiya

IPC分类号： G03G15/00 ,  C08K3/36 ,  C08L9/02 ,  C08L21/00 ,  C08L71/03 ,  F16C13/00 ,  G03G15/02 ,  G03G15/08 ,  G03G15/16

CPC分类号： G03G15/0233 ,  G03G2215/0634 ,  G03G2215/1614 ,  Y10T428/31826

摘要： An electrically conductive roll includes a shaft body and at least a conductive elastic layer formed by extrusion on an outer circumferential surface of the shaft body. The conductive elastic layer is formed from at least one conductive rubber composition which includes a rubber material, a thermoplastic resin having crosslinkable double bonds and a melting point in a range from 40° C. to 100° C., and at least one conductive agent. The thermoplastic resin is included in an amount of 5 to 50 wt. % of a total amount of the rubber material and the thermoplastic resin.

摘要翻译： 导电辊包括轴体和至少一个通过在轴体的外圆周表面上挤压形成的导电弹性层。 导电弹性层由至少一种导电橡胶组合物形成，该组合物包括橡胶材料，具有可交联双键的热塑性树脂和熔点在40℃至100℃的范围内，以及至少一种导电剂 。 热塑性树脂的含量为5〜50重量％。 橡胶材料和热塑性树脂的总量的百分比。