公开(公告)号：US4954946A

公开(公告)日：1990-09-04

申请号：US453088

申请日：1989-12-21

申请人： Paul J. Natusch ,  Eugene L. Yu ,  David C. Senerchia ,  John F. Henry, Jr., deceased

发明人： Paul J. Natusch ,  Eugene L. Yu ,  David C. Senerchia ,  John F. Henry, Jr., deceased

IPC分类号： G06F13/16 ,  G06F13/00

CPC分类号： G06F13/1615

摘要： For use in a data processing system, a main memory subsystem includes a plurality of memory boards for storing groups of logic signals. Each memory board includes an plurality of array units. Each array unit is adapted to store a group of logic signals that is equivalent in size to the field of data logic signals transferred on the system bus and has an address structure so that each addressable data signal group can be stored in a single array. The address field of each array unit is further adapted so that the probability of interfering activity in each array is low. The arrays are adapted process data signal groups independently, thus, activity involving several arrays can take place simultaneously. The memory subsystem is structured to provide a pipeline types of overlapping activity so that activity involving several array units can be in progress simultaneously. Because the manipulation of the storage cells requires the most amounts of time in the memory unit, and because the arrays are performing this activity independently for each signal group, then the memory unit can be adapted to process the signal groups applied sequentially to the system without delay in nonexceptional circumstances, the most general exceptional circumstance being the masked write operation.

摘要翻译： 为了在数据处理系统中使用，主存储器子系统包括用于存储逻辑信号组的多个存储器板。 每个存储器板包括多个阵列单元。 每个阵列单元适于存储一组逻辑信号，其大小与在系统总线上传送的数据逻辑信号的字段相当，并且具有地址结构，使得每个可寻址数据信号组可以存储在单个阵列中。 每个阵列单元的地址字段进一步被适配，使得每个阵列中的干扰活动的概率很低。 阵列是独立的适应过程数据信号组，因此，可以同时进行涉及几个阵列的活动。 存储器子系统被构造为提供重叠活动的流水线类型，使得涉及若干阵列单元的活动可以同时进行。 由于存储单元的操作需要在存储器单元中大量的时间，并且由于阵列对于每个信号组独立地执行该活动，因此存储器单元可以适于处理顺序地施加到系统的信号组而无需 在非感知情况下的延迟，最常见的例外情况是屏蔽写操作。

公开(公告)号：US4791552A

公开(公告)日：1988-12-13

申请号：US823951

申请日：1986-01-29

申请人： Paul J. Natusch ,  David C. Senerchia ,  John F. Henry, Jr., deceased

发明人： Paul J. Natusch ,  David C. Senerchia ,  John F. Henry, Jr., deceased

IPC分类号： G06F12/06 ,  G11C8/18 ,  G06F12/00

CPC分类号： G06F12/0607 ,  G11C8/18

摘要： Apparatus is disclosed for selecting a group of address signals to be applied to a memory unit array and for applying the address signals to the memory unit array to permit the activity associated with the address signals to be completed. The apparatus generates a multiplicity of signals controlling a latch-type buffer storage unit. The first generated signal insures that the signal controlling the buffer storage unit is active during application of the address signals to the system bus. The second generated signal overlaps the first generated signal and extends the signal controlling the buffer storage unit a small amount. The third generated signal overlaps the second generated signal and extends the signal controlling the buffer storage unit for the period of time necessary to utilize the memory unit array.

摘要翻译： 公开了用于选择要应用于存储器单元阵列的一组地址信号并将地址信号施加到存储器单元阵列以允许与地址信号相关联的活动完成的装置。 该装置产生控制锁存型缓冲存储单元的多个信号。 第一个产生的信号确保在将地址信号应用于系统总线时控制缓冲存储单元的信号有效。 第二产生的信号与第一生成信号重叠，并且将控制缓冲存储单元的信号扩展到少量。 第三产生的信号与第二个产生的信号重叠，并扩展控制缓冲存储单元的信号达到利用存储单元阵列所需的时间。