公开(公告)号：US5023692A

公开(公告)日：1991-06-11

申请号：US447330

申请日：1989-12-07

申请人： Paul J. Wodarczyk ,  Carl F. Wheatley, Jr. ,  John M. S. Neilson ,  Frederich P. Jones

发明人： Paul J. Wodarczyk ,  Carl F. Wheatley, Jr. ,  John M. S. Neilson ,  Frederich P. Jones

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/04 ,  H01L27/088 ,  H03K17/08

CPC分类号： H01L27/0251

摘要： The present invention relates to a power MOS transistor having a current limiting circuit incorporated in the same substrate as the transistor. The power MOS transistor includes a drain region extending through the substrate between opposed first and second surfaces, a plurality of body regions in the substrate at the first surface, a separate source region in the substrate at the first surface within each body region and a channel extending across each body region between its junction with its respective source region and its junction with the drain region. A conductive gate is over and insulated from the first surface and extends over the channel regions. A first conductive electrode extends over and is insulated from the gate and contacts a first portion of the source regions. A second conductive electrode extends over and is insulated from the gate and contacts a second portion of the source regions. The second portion contains a smaller number of the source regions than the first portion. The current limiting circuit includes a bipolar transistor formed in a well region in the substrate, a zener diode formed in a second well region in the substrate and two resistors formed over and insulated from the first surface. The current limiting circuit is connected between the second portion of the source regions and the gate so as to reduce the power through the circuit.

摘要翻译： 本发明涉及一种具有与晶体管相同的衬底中的限流电路的功率MOS晶体管。 功率MOS晶体管包括在相对的第一和第二表面之间延伸穿过衬底的漏极区域，在第一表面处的衬底中的多个体区域，在每个体区域内的第一表面处的衬底中的单独源极区域和沟道 在其与其各自的源极区域的连接点及其与漏极区域的连接处的每个体区域之间延伸。 导电栅极与第一表面结合并且绝缘，并且在沟道区域上延伸。 第一导电电极延伸并且与栅极绝缘并接触源极区域的第一部分。 第二导电电极延伸并且与栅极绝缘并且接触源极区域的第二部分。 第二部分包含比第一部分少的源区域。 电流限制电路包括形成在衬底的阱区中的双极晶体管，形成在衬底中的第二阱区中的齐纳二极管和形成在第一表面上并与第一表面绝缘的两个电阻。 电流限制电路连接在源区的第二部分和栅极之间，以便减小通过电路的功率。