公开(公告)号：US20070076004A1

公开(公告)日：2007-04-05

申请号：US11242149

申请日：2005-10-04

申请人： Paul Wallner ,  Yukio Fukuzo ,  Christian Sichert ,  Paul Schmolz

发明人： Paul Wallner ,  Yukio Fukuzo ,  Christian Sichert ,  Paul Schmolz

IPC分类号： G06T1/00

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.

摘要翻译： 信号作为串行信号帧传送的半导体存储器芯片包括提供存储器核心和接收接口之间的接口的帧解码器。 帧解码器包括用于根据解码的命令类型对包括在帧中的命令的类型进行解码的命令类型解码器，用于调度和准备用于核心的单个命令的存储器命令评估器/生成器，中间数据缓冲器命令评估器/生成器 用于调度和准备中间数据缓冲器的控制信号，以及用于准备和调度系统命令的系统命令评估器/发生器。 这些系统命令提供定时参数，以确保一帧内或帧之间的连续命令之间的时间间隔，并存储在系统模式寄存器中。 帧解码器的操作由帧时钟或同步解码器时钟信号进行边沿同步，该时钟信号与该帧时钟信号相对齐。