公开(公告)号：US06216099B1

公开(公告)日：2001-04-10

申请号：US08924090

申请日：1997-09-05

申请人： Peng Fang ,  Sunil Shabde

发明人： Peng Fang ,  Sunil Shabde

IPC分类号： G06F1750

CPC分类号： G01R31/31704

摘要： A test system and methodology to improve the performance and reliability of critical paths including stacked NAND gates with sub-minimum channel transistors employs one or more inverter based ring oscillators to generate reliability data. The reliability data is used to calibrate an aged transistor model, which describes the hot carrier reliability of sub-minimum channel length transistors. A computer simulation uses the calibrated, aged transistor model to simulate the critical path circuitry including the stacked NAND gates.

摘要翻译： 提高关键路径的性能和可靠性的测试系统和方法，包括具有次最小通道晶体管的堆叠NAND门采用一个或多个基于逆变器的环形振荡器来产生可靠性数据。 可靠性数据用于校准老化的晶体管模型，其描述了次最小沟道长度晶体管的热载流子可靠性。 计算机模拟使用经校准的老化晶体管模型来模拟包括堆叠NAND门的关键路径电路。