公开(公告)号：US08442691B2

公开(公告)日：2013-05-14

申请号：US12811835

申请日：2009-01-13

申请人： Geert Willem Van Der Veen ,  Peter Deixler ,  Cornelis Jojakim Jalink ,  Paul Stravers

发明人： Geert Willem Van Der Veen ,  Peter Deixler ,  Cornelis Jojakim Jalink ,  Paul Stravers

IPC分类号： G06F19/00 ,  H05B37/00

CPC分类号： H05B37/0254

摘要： Light source having a plurality of light elements (207) and a control system for controlling the light elements. The control system comprises a plurality of light element controllers (213), each connected to a respective light element (207), and arranged to obtain light element data; and a bus interface (203), which is connected to the light element controllers (213) via a light source bus (209). The bus interface (203) provides the light element controllers (213) with a general command, and the light element controllers generate light element drive signals on basis of the general command and the light element data.

摘要翻译： 光源具有多个光元件（207）和用于控制光元件的控制系统。 控制系统包括多个光元件控制器（213），每个光元件控制器连接到相应的光元件（207），并被布置成获得光元件数据; 以及经由光源总线（209）连接到所述光元件控制器（213）的总线接口（203）。 总线接口（203）为光元件控制器（213）提供通用命令，并且光元件控制器基于通用命令和光元件数据产生光元件驱动信号。

公开(公告)号：US20100079091A1

公开(公告)日：2010-04-01

申请号：US12517367

申请日：2007-12-07

申请人： Peter Deixler ,  Cornelis Jojakim Jalink ,  Paul Stravers

发明人： Peter Deixler ,  Cornelis Jojakim Jalink ,  Paul Stravers

IPC分类号： H05B37/00

CPC分类号： H05B37/0254

摘要： This invention relates to a light source (201) having a plurality of light elements (207) and a control system for controlling the, light elements. The control system comprises a plurality of light element controllers (213), each connected to a respective light element (207), and arranged to obtain light element data; and a bus interface (203), which is connected to the light element controllers (213) via a light source bus (209). The bus interface (203) provides the light element controllers (213) with a general command, and the light element controllers (213) generate light element drive signals on basis of the general command and the light element data.

摘要翻译： 本发明涉及具有多个光元件（207）的光源（201）和用于控制光元件的控制系统。 控制系统包括多个光元件控制器（213），每个光元件控制器连接到相应的光元件（207），并被布置成获得光元件数据; 以及经由光源总线（209）连接到所述光元件控制器（213）的总线接口（203）。 总线接口（203）为光元件控制器（213）提供通用命令，并且光元件控制器（213）基于通用命令和光元件数据产生光元件驱动信号。

公开(公告)号：US08412354B2

公开(公告)日：2013-04-02

申请号：US12517367

申请日：2007-12-07

申请人： Peter Deixler ,  Cornelis Jojakim Jalink ,  Paul Stravers

发明人： Peter Deixler ,  Cornelis Jojakim Jalink ,  Paul Stravers

IPC分类号： G05B11/01

CPC分类号： H05B37/0254

摘要： A light source having a plurality of light elements and a control system for controlling the light elements. The control system comprises a plurality of light element controllers, each connected to a respective light element, and arranged to obtain light element data; and a bus interface, which is connected to the light element controllers via a light source bus. The bus interface provides the light element controllers with a general command, and the light element controllers generate light element drive signals on basis of the general command and the light element data.

摘要翻译： 具有多个光元件的光源和用于控制光元件的控制系统。 控制系统包括多个光元件控制器，每个光元件控制器连接到相应的光元件，并被布置成获得光元件数据; 以及通过光源总线连接到光控制器的总线接口。 总线接口为光元件控制器提供通用命令，并且光元件控制器基于通用命令和光元件数据产生光元件驱动信号。

公开(公告)号：US20100277079A1

公开(公告)日：2010-11-04

申请号：US12811835

申请日：2009-01-13

申请人： Geert Willem Van Der Veen ,  Peter Deixler ,  Cornelis Jojakim Jalink ,  Paul Stravers

发明人： Geert Willem Van Der Veen ,  Peter Deixler ,  Cornelis Jojakim Jalink ,  Paul Stravers

IPC分类号： H05B37/02

CPC分类号： H05B37/0254

摘要： Light source having a plurality of light elements (207) and a control system for controlling the light elements. The control system comprises a plurality of light element controllers (213), each connected to a respective light element (207), and arranged to obtain light element data; and a bus interface (203), which is connected to the light element controllers (213) via a light source bus (209). The bus interface (203) provides the light element controllers (213) with a general command, and the light element controllers generate light element drive signals on basis of the general command and the light element data.

摘要翻译： 光源具有多个光元件（207）和用于控制光元件的控制系统。 控制系统包括多个光元件控制器（213），每个光元件控制器连接到相应的光元件（207），并被布置成获得光元件数据; 以及经由光源总线（209）连接到所述光元件控制器（213）的总线接口（203）。 总线接口（203）为光元件控制器（213）提供通用命令，并且光元件控制器基于通用命令和光元件数据产生光元件驱动信号。

公开(公告)号：US07769937B2

公开(公告)日：2010-08-03

申请号：US11817057

申请日：2006-02-21

申请人： Jayram Moorkanikara Nageswaran ,  Paul Stravers

发明人： Jayram Moorkanikara Nageswaran ,  Paul Stravers

IPC分类号： G06F13/26

CPC分类号： G06F13/26

摘要： A data processing system includes a first interrupt controller with an interrupt source interface, an interrupt controller interface, a prioritizer, and an interrupt controller output. The data processing system further includes a processing unit providing an interrupt controller interface. Interrupt requests generated by a first plurality of interrupt sources, a second selected interrupt request, a second priority signal, and a second interrupt source index signal generated by a second interrupt controller are received by the first interrupt controller. From the plurality of interrupt requests and the second selected interrupt request, a first single interrupt request is selected and transmitted to the processing unit along with a first priority signal, and a first index signal. The processing unit initiates an appropriate interrupt service routine on the basis of said first index signal.

摘要翻译： 数据处理系统包括具有中断源接口的第一中断控制器，中断控制器接口，优先级排序器和中断控制器输出。 数据处理系统还包括提供中断控制器接口的处理单元。 由第一中断控制器接收由第一多个中断源产生的中断请求，由第二中断控制器产生的第二所选中断请求，第二优先级信号和第二中断源索引信号。 从多个中断请求和第二选择的中断请求，选择第一单个中断请求并将其与第一优先级信号和第一索引信号一起发送到处理单元。 处理单元基于所述第一索引信号发起适当的中断服务程序。

公开(公告)号：US06851044B1

公开(公告)日：2005-02-01

申请号：US09505986

申请日：2000-02-16

申请人： Paul Stravers

发明人： Paul Stravers

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/38 ,  G06F9/42 ,  G06F9/46 ,  G06F9/48 ,  G06F15/00

CPC分类号： G06F9/3867 ,  G06F9/3826 ,  G06F9/3861

摘要： An instruction execution device and method are disclosed for reducing register write traffic within a processor with exception routines. The instruction execution device includes an instruction pipeline for producing a result for an instruction, wherein the exception routines may interrupt the instruction pipeline a random intervals, a register file that includes at least one write port for storing the result, a bypass circuit for allowing access to the result, a means for indicating whether the result is used by only one other instruction, a register file control for preventing the result from being stored in the write port when the result has been accessed via the bypass circuit and is used by only one other instruction, a First in First out (FIFO) buffer for storing the result and a FIFO control for writing the contents of the FIFO buffer to the register file when an exception occurs.

摘要翻译： 公开了一种用于在具有异常例程的处理器内减少寄存器写入流量的指令执行装置和方法。 指令执行装置包括用于产生用于指令的结果的指令流水线，其中异常例程可以中断指令流水线随机间隔，包括用于存储结果的至少一个写入端口的寄存器文件，允许访问的旁路电路 结果是用于指示结果是否仅被一个其他指令使用的装置，当通过旁路电路访问结果时用于防止结果被存储在写入端口中的寄存器文件控制，并且仅由一个 其他指令，用于存储结果的先进先出（FIFO）缓冲器和当异常发生时将FIFO缓冲器的内容写入寄存器文件的FIFO控制。

公开(公告)号：US09141350B2

公开(公告)日：2015-09-22

申请号：US13641830

申请日：2011-04-20

申请人： Paul Stravers ,  Jos Van Eijndhoven ,  Martijn Rutten ,  Alexey Rodriguez ,  Wouter Swierstra ,  Maurice Kastelijn

发明人： Paul Stravers ,  Jos Van Eijndhoven ,  Martijn Rutten ,  Alexey Rodriguez ,  Wouter Swierstra ,  Maurice Kastelijn

IPC分类号： G06F9/44 ,  G06F9/45

CPC分类号： G06F8/35 ,  G06F8/433

摘要： A method of generating an embedded system (4999) from an original computer program (996) which embedded system (4999) provides a parallellized hardware (4598) and software (4599) implementation of the original computer program (996), which parallellized implementation (4598, 4599) satisfies one or more criteria regarding hardware constraints of the embedded system (4999).The system provides partitioning of functionality from the original computer program (996) using structural and behavioral program models and detects streaming and memory dependencies to improve the partitioning, relying on added indications of source lines and variables in said original computer program to relate partitions and dependencies in the program model with locations in the original program source code.

摘要翻译： 一种从原始计算机程序（996）生成嵌入式系统（4999）的方法，嵌入式系统（4999）提供并行化实现的原始计算机程序（996）的并行化硬件（4598）和软件（4599） 4598,45599）满足关于嵌入式系统的硬件约束的一个或多个标准（4999）。 该系统使用结构和行为程序模型提供来自原始计算机程序（996）的功能分区，并且检测流和存储器相关性以改进分区，依赖于所述原始计算机程序中的源线和变量的附加指示来关联分区和依赖性 在具有原始程序源代码的位置的程序模型中。

公开(公告)号：US20130080993A1

公开(公告)日：2013-03-28

申请号：US13641830

申请日：2011-04-04

申请人： Paul Stravers ,  Jos Van Eijndhoven ,  Martijn Rutten ,  Alexey Rodriguez ,  Wouter Swierstra ,  Maurice Kastelijn

发明人： Paul Stravers ,  Jos Van Eijndhoven ,  Martijn Rutten ,  Alexey Rodriguez ,  Wouter Swierstra ,  Maurice Kastelijn

IPC分类号： G06F9/44

CPC分类号： G06F8/35 ,  G06F8/433

摘要： A method of generating an embedded system (4999) from an original computer program (996) which embedded system (4999) provides a parallellized hardware (4598) and software (4599) implementation of the original computer program (996), which parallellized implementation (4598, 4599) satisfies one or more criteria regarding hardware constraints of the embedded system (4999). The system provides partitioning of functionality from the original computer program (996) using structural and behavioral program models and detects streaming and memory dependencies to improve the partitioning, relying on added indications of source lines and variables in said original computer program to relate partitions and dependencies in the program model with locations in the original program source code.

摘要翻译： 一种从原始计算机程序（996）生成嵌入式系统（4999）的方法，嵌入式系统（4999）提供并行化实现的原始计算机程序（996）的并行化硬件（4598）和软件（4599） 4598,45599）满足关于嵌入式系统的硬件约束的一个或多个标准（4999）。 该系统使用结构和行为程序模型提供来自原始计算机程序（996）的功能分区，并且检测流和存储器相关性以改进分区，依赖于所述原始计算机程序中的源线和变量的附加指示来关联分区和依赖性 在程序模型中具有原始程序源代码中的位置。

公开(公告)号：US06643739B2

公开(公告)日：2003-11-04

申请号：US09805384

申请日：2001-03-13

申请人： Jan-Willem Van De Waerdt ,  Paul Stravers

发明人： Jan-Willem Van De Waerdt ,  Paul Stravers

IPC分类号： G06F1200

CPC分类号： G06F12/0864 ,  G06F9/3824 ,  G06F9/3832 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

摘要： A way prediction scheme for a partitioned cache is based on the contents of instructions that use indirect addressing to access data items in memory. The contents of indirect-address instructions are directly available for use, without a memory address computation, and a prediction scheme based on this directly available information is particularly well suited for a pipeline architecture. Indirect addressing instructions also provide a higher-level abstraction of memory accesses, and are likely to be more indicative of relationships among data items, as compared to the absolute address of the data items. In a preferred embodiment, the base register that is contained in the indirect address instruction provides an index to a way-prediction table for an n-way associative cache. Data items that are indirectly addressed using the same base register are likely to be related, and thus predicting a particular way in an n-way associative memory based on the base register of an indirect address instruction is likely to result in a cache-hit, thereby reducing the energy consumption associated with accessing all ways in the cache.

公开(公告)号：US09081928B2

公开(公告)日：2015-07-14

申请号：US13375754

申请日：2010-06-01

申请人： Jos Van Eijndhoven ,  Tommy Kamps ,  Maurice Kastelijn ,  Martijn Rutten ,  Paul Stravers

发明人： Jos Van Eijndhoven ,  Tommy Kamps ,  Maurice Kastelijn ,  Martijn Rutten ,  Paul Stravers

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F8/433 ,  G06F8/456 ,  G06F17/505 ,  G06F2217/86

摘要： A computer-implemented method of automatically generating an embedded system on the basis of an original computer program, comprising analyzing the original computer program, comprising a step of compiling the original computer program into an executable to obtain data flow graphs with static data dependencies and a step of executing the executable using test data to provide dynamic data dependencies as communication patterns between load and store operations of the original computer program, and a step of transforming the original computer program into an intermediary computer program that exhibits multi-threaded parallelism with inter-thread communication, which comprises identifying at least one static and/or dynamic data dependency that crosses a thread boundary and converting said data dependency into a buffered communication channel with read/write access.

摘要翻译： 一种基于原始计算机程序自动生成嵌入式系统的计算机实现的方法，包括分析原始计算机程序，包括将原始计算机程序编译成可执行程序以获得具有静态数据依赖性的数据流图的步骤，以及 使用测试数据执行可执行程序以提供动态数据依赖性作为原始计算机程序的加载和存储操作之间的通信模式的步骤，以及将原始计算机程序变换成具有多线程并行性的中间计算机程序的步骤， 线程通信，其包括识别跨越线程边界的至少一个静态和/或动态数据依赖性，并将所述数据依赖性转换为具有读/写访问的缓冲通信信道。