-
1.发明申请Method and system for determining total code execution time in a data processor 失效用于确定数据处理器中总代码执行时间的方法和系统公开(公告)号：US20050166202A1
公开(公告)日：2005-07-28
申请号：US10500708
申请日：2003-02-06
申请人： Peter Gerell , Thomas Stromqvist
发明人： Peter Gerell , Thomas Stromqvist
CPC分类号： G06F8/457
摘要： The invention refers to a method and a processing system for a communications network. The method comprises the step of receiving a program code, comprising a plurality of instructions for the communications network, dividing the program code into a plurality of sequences (7), defining, based on the program code, a plurality of relocation objects (10), each corresponding to a dependency relationship between two or more of the sequences (7), and allocating the sequences (7) to a processor instruction memory (4). Preferably, at least one directed graph is formed, based on at least some of the sequences (7) and at least some of the relocation objects (10), and a longest execution path through the directed graph is determined. Sequences (7) in the instruction memory (4) can be moved and state preserving operations (NOP) can be entered, so as to make at least two execution paths equally long.
摘要翻译： 本发明涉及通信网络的方法和处理系统。 该方法包括接收程序代码的步骤，包括用于通信网络的多个指令，将程序代码分成多个序列（7），根据程序代码定义多个重定位对象（10） ，每个对应于两个或更多个序列（7）之间的依赖关系，并将序列（7）分配给处理器指令存储器（4）。 优选地，基于至少一些序列（7）和至少一些重定位对象（10）形成至少一个有向图，并且确定通过有向图的最长执行路径。 可以移动指令存储器（4）中的顺序（7），并且可以输入状态保持操作（NOP），以便使至少两个执行路径同样长。
-
2.发明授权Method and system for determining total code execution time in a data processor 失效用于确定数据处理器中总代码执行时间的方法和系统公开(公告)号：US07661100B2
公开(公告)日：2010-02-09
申请号：US10500708
申请日：2003-02-06
申请人： Peter Gerell , Thomas Stromqvist
发明人： Peter Gerell , Thomas Stromqvist
CPC分类号： G06F8/457
摘要： A method and a processing system for a communications network, including receiving a program code including multiple instructions for the communications network dividing the program into multiple sequences, defining multiple relocation objects, each corresponding to a dependency relationship between two or more of the sequences, and allocating the sequences to a processor instruction memory.
摘要翻译： 一种用于通信网络的方法和处理系统，包括接收包括用于通信网络的多个指令的程序代码，所述通信网络将程序划分为多个序列，定义多个重定位对象，每个对应于两个或更多个序列之间的依赖关系，以及 将序列分配给处理器指令存储器。
-
公开(公告)号：US07644190B2
公开(公告)日：2010-01-05
申请号：US10521198
申请日：2003-07-09
IPC分类号： G06F3/00
CPC分类号： G06F9/3879 , G06F15/7832 , H04L49/90 , H04L49/9089
摘要： The present invention relates to a method and apparatus for pipelined processing of data packets. A pipeline in a processor comprises an access point providing simultaneous access to one or more devices, said devices mainly for data processing operations not provided by the pipeline. The access point comprises at least one FIFO store for storing data entering the access point, a response FIFO store for storing responses received from the device(s), and a synchronization mechanism adapted to synchronize the fetching of the first entry in the FIFO store(s) and the first entry in the response FIFO store. The synchronization mechanism could advantageously be a fixed time delay mechanism. When the fixed time initiated by the fixed time delay mechanism has elapsed, the first response in the response FIFO store is merged into the data stored in the first entry in the FIFO store(s) for storing data entering the access point.
摘要翻译： 本发明涉及数据包流水线处理的方法和装置。 处理器中的管线包括提供对一个或多个设备的同时访问的接入点，所述设备主要用于未由管道提供的数据处理操作。 接入点包括用于存储进入接入点的数据的至少一个FIFO存储器，用于存储从设备接收的响应的响应FIFO存储器，以及适于同步FIFO存储器中的第一条目的获取的同步机制（ s）和响应FIFO存储中的第一个条目。 同步机制可以有利地是固定的时间延迟机制。 当由固定时间延迟机制启动的固定时间过去时，响应FIFO存储器中的第一响应被合并到存储在FIFO存储器中的第一条目中的数据，用于存储进入接入点的数据。
-
公开(公告)号：US20060129718A1
公开(公告)日：2006-06-15
申请号：US10521198
申请日：2003-07-09
CPC分类号： G06F9/3879 , G06F15/7832 , H04L49/90 , H04L49/9089
摘要： The present invention relates to a method and apparatus for pipelined processing of data packets. A pipeline in a processor comprises an access point providing simultaneous access to one or more devices, said devices mainly for data processing operations not provided by the pipeline. The access point comprises at least one FIFO store for storing data entering the access point, a response FIFO store for storing responses received from the device(s), and a synchronisation mechanism adapted to synchronise the fetching of the first entry in the FIFO store(s) and the first entry in the response FIFO store. The synchronisation mechanism could advantageously be a fixed time delay mechanism. When the fixed time initiated by the fixed time delay mechanism has elapsed, the first response in the response FIFO store is merged into the data stored in the first entry in the FIFO store(s) for storing data entering the access point.
摘要翻译： 本发明涉及数据包流水线处理的方法和装置。 处理器中的管线包括提供对一个或多个设备的同时访问的接入点，所述设备主要用于未由管道提供的数据处理操作。 接入点包括用于存储进入接入点的数据的至少一个FIFO存储器，用于存储从设备接收的响应的响应FIFO存储器，以及适于同步FIFO存储器中的第一条目的获取的同步机制（ s）和响应FIFO存储中的第一个条目。 同步机制可以有利地是固定的时间延迟机制。 当由固定时间延迟机制启动的固定时间过去时，响应FIFO存储器中的第一响应被合并到存储在FIFO存储器中的第一条目中的数据，用于存储进入接入点的数据。
-
公开(公告)号：US07397798B2
公开(公告)日：2008-07-08
申请号：US10478377
申请日：2001-05-21
IPC分类号： H04L12/56
CPC分类号： H04L49/602 , H04L49/3063
摘要： Method in a pipeline processing stage in a processor, includes the steps of: receiving a first block from a first register and a first execution parameter associated with the first block from a second register, the execution parameter having a first value; inspecting a set of data being at least a part of the first block; and, if the set of data differs from a predetermined condition, storing a second execution parameter on a third register and a third execution parameter on the second register, where the second execution parameter has a second value and is associated with the first block and the third execution parameter has the first value and will be associated with a second block. The invention also relates to the pipeline processor, a module, an integrated circuit and a computer unit.
摘要翻译： 处理器中的流水线处理阶段的方法包括以下步骤：从第一寄存器接收第一块和与第一块相关联的第一执行参数，所述执行参数具有第一值; 检查作为所述第一块的至少一部分的一组数据; 并且如果所述数据集合与预定条件不同，则在所述第二寄存器上将第二执行参数存储在第三寄存器和第三执行参数上，其中所述第二执行参数具有第二值并且与所述第一块相关联， 第三执行参数具有第一个值并将与第二个块相关联。 本发明还涉及流水线处理器，模块，集成电路和计算机单元。
-
-
-
-
搜索结果
5 条记录 (耗时 0.011 秒)
