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公开(公告)号:US20240348562A1
公开(公告)日:2024-10-17
申请号:US18757825
申请日:2024-06-28
Applicant: Intel Corporation
Inventor: Yotam Nizri , Wing Cheung , Thang Quang Nguyen , Kenneth Keels , Noam Elati
IPC: H04L49/00 , H04L49/9005
CPC classification number: H04L49/3063 , H04L49/9005 , H04L49/70
Abstract: A shared networking pipeline is implemented by a network interface device and shared by a plurality of host devices. A pool of shared buffers of a network interface device correspond to one or more stages in the pipeline and are configured to allocate entries to the plurality of host devices based on the respective shares of the shared packet processing pipeline. Data is buffered associated with traffic of a first one of the plurality of host devices in a first subset of shared buffers, where the traffic is to proceed from a first stage to a second stage in the shared packet processing pipeline, and the data is associated with processing of the traffic by the second stage. Forward progress of the traffic is to be prevented from the first stage to the second stage when the first subset of entries are occupied.
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2.
公开(公告)号:US12088465B2
公开(公告)日:2024-09-10
申请号:US17573547
申请日:2022-01-11
Applicant: Pensando Systems Inc.
Inventor: Sameer Kittur Subrahmanya , Krishna Doddapaneni
IPC: H04L41/082 , H04L41/12 , H04L49/00
CPC classification number: H04L41/082 , H04L41/12 , H04L49/3063
Abstract: A network appliance can continue operation at a degraded level during an upgrade that requires less free pipeline memory than other upgrade techniques. The network appliance has a control plane and has a data plane with a packet processing pipeline circuit. Before the upgrade, the control plane has configured the packet processing pipeline circuit to process a network flow. The packet processing pipeline may be halted in order to perform a pipeline upgrade during which the packet processing pipeline circuit's pipeline memory is cleared. The packet processing pipeline circuit is restarted after the pipeline upgrade after which the control plane can reconfigure the packet processing pipeline circuit to process the network flow. The packet processing pipeline circuit can therefore process the network flow after the pipeline upgrade.
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公开(公告)号:US12028215B2
公开(公告)日:2024-07-02
申请号:US18088763
申请日:2022-12-26
Applicant: Nicira, Inc.
Inventor: W. Andrew Lambeth , Teemu Koponen , Martin Casado
IPC: H04L12/46 , G06F15/173 , H04L41/0816 , H04L41/0853 , H04L41/0893 , H04L41/0896 , H04L45/00 , H04L45/02 , H04L45/586 , H04L47/783 , H04L49/00 , H04L49/1546 , H04L61/5007 , G06F11/07 , H04L101/622
CPC classification number: H04L41/0893 , G06F15/17312 , H04L12/4633 , H04L41/0816 , H04L41/0853 , H04L41/0896 , H04L45/00 , H04L45/02 , H04L45/586 , H04L47/783 , H04L49/00 , H04L49/1546 , H04L49/3063 , H04L49/70 , H04L61/5007 , G06F11/07 , H04L2101/622
Abstract: A method for managing a managed forwarding element (MFE) that forwards data in a network. A network controller publishes, to the MFE, a first set of data for configuring the MFE to perform a set of forwarding operations. The network controller collects, from the MFE, a second set of data regarding current operational state of the MFE. The network controller identifies a difference between a desired operational state of the MFE maintained by the network controller and the collected current operational state of the MFE. Based on the identified difference, the network controller publishes a new third set of data for configuring the MFE to adjust the current operational state of the MFE to the desired state.
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公开(公告)号:US11956150B1
公开(公告)日:2024-04-09
申请号:US17328269
申请日:2021-05-24
Applicant: T-MOBILE INNOVATIONS LLC
Inventor: Brian Waters
CPC classification number: H04L45/74 , H04L49/3063 , H04L67/14
Abstract: Programmable networking devices configured to perform various packet processing functions for packet filtration, control and user plane separation (CUPS), user plane function (UPF), pipeline processing, etc. IPsec is utilized to secure control and data packets traversing the programmable networking device. Field-programmable gate arrays (FPGAs) are configured with one or more host servers and software-based network interfaces (softMAC).
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公开(公告)号:US11916800B2
公开(公告)日:2024-02-27
申请号:US16912553
申请日:2020-06-25
Applicant: Intel Corporation
Inventor: David Arditti Ilitzky , John Greth , Robert Southworth , Karl S. Papadantonakis , Bongjin Jung , Arvind Srinivasan
IPC: H04L47/283 , H04L43/087 , H04L43/16 , H04L49/00 , H04L47/125 , H04L49/25 , H04L49/90 , H04L47/62
CPC classification number: H04L47/283 , H04L43/087 , H04L43/16 , H04L47/125 , H04L47/6205 , H04L49/25 , H04L49/3063 , H04L49/9042
Abstract: Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer. In some examples, a fetch scheduler is used to adapt an amount of interface overspeed to reduce packet fetching latency while attempting to prevent fabric saturation based on a switch fabric load level, wherein the fetch scheduler is to control the jitter threshold level for the buffer by forcing a jitter threshold level based on switch fabric load level and latency profile of the switch fabric.
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6.
公开(公告)号:US20230388184A1
公开(公告)日:2023-11-30
申请号:US18195678
申请日:2023-05-10
Applicant: Barefoot Networks, Inc.
Inventor: Remy Chang
IPC: H04L41/0833 , G06F1/3234 , G06F1/04 , H04L45/745 , H04L49/25 , H04L49/00 , H04L45/00 , G06F1/20 , G06F1/32 , G06F3/06 , G06F13/16 , H04L49/40 , H04L49/50 , H04L49/505
CPC classification number: H04L41/0833 , G06F1/3234 , G06F1/04 , H04L45/745 , H04L49/25 , H04L49/3063 , H04L45/38 , G06F1/206 , G06F1/32 , G06F3/0613 , G06F3/065 , G06F3/067 , G06F13/161 , G06F13/1642 , H04L49/40 , H04L49/501 , H04L49/505 , H04L69/22
Abstract: Some embodiments of the invention provide a network forwarding element that can be dynamically reconfigured to adjust its data message processing to stay within a desired operating temperature or power consumption range. In some embodiments, the network forwarding element includes (1) a data-plane forwarding circuit (“data plane”) to process data tuples associated with data messages received by the IC, and (2) a control-plane circuit (“control plane”) for configuring the data plane forwarding circuit. The data plane includes several data processing stages to process the data tuples. The data plane also includes an idle-signal injecting circuit that receives from the control plane configuration data that the control plane generates based on the IC's temperature. Based on the received configuration data, the idle-signal injecting circuit generates idle control signals for the data processing stages. Each stage that receives an idle control signal enters an idle state during which the majority of the components of that stage do not perform any operations, which reduces the power consumed and temperature generated by that stage during its idle state.
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公开(公告)号:US11831567B1
公开(公告)日:2023-11-28
申请号:US17946902
申请日:2022-09-16
Applicant: Marvell Asia Pte, Ltd.
Inventor: William Brad Matthews , Puneet Agarwal , Ajit Kumar Jain
IPC: H04L49/901 , H04L49/00 , H04L49/9047
CPC classification number: H04L49/901 , H04L49/3027 , H04L49/3063 , H04L49/9047
Abstract: Link data is stored in a distributed link descriptor memory (“DLDM”) including memory instances storing protocol data unit (“PDU”) link descriptors (“PLDs”) or cell link descriptors (“CLDs”). Responsive to receiving a request for buffering a current transfer data unit (“TDU”) in a current PDU, a current PLD is accessed in a first memory instance in the DLDM. It is determined whether any data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD. If no data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD, a current CLD is accessed in a second memory instance in the plurality of memory instances of the same DLDM. Current address information in connection with the current TDU is stored in an address data field within the current CLD.
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公开(公告)号:US11799800B2
公开(公告)日:2023-10-24
申请号:US17580596
申请日:2022-01-20
Applicant: Nicira, Inc.
Inventor: Ronghua Zhang , Ganesan Chandrashekhar , Sreeram Ravinoothala , Kai-Wei Fan
IPC: H04L49/25 , H04L12/66 , H04L45/64 , H04L69/321 , H04L12/46 , H04L41/5041 , H04L45/74 , H04L67/63 , H04L67/568 , H04L67/1001 , H04L45/00 , H04L49/00 , H04L45/02 , H04L45/42 , H04L45/44 , H04L41/0654 , H04L45/122 , H04L45/745 , H04L61/2585 , H04L41/14 , H04L69/326 , H04L69/329 , H04L47/19 , H04L49/90 , H04L45/586 , H04L45/302 , H04L43/08 , H04L43/106 , H04L49/354 , H04L67/1038 , H04L61/103 , H04L61/2503 , H04L41/50 , H04L45/28 , H04L101/663 , H04L67/1095
CPC classification number: H04L49/25 , H04L12/4633 , H04L12/4654 , H04L12/66 , H04L41/0654 , H04L41/145 , H04L41/5041 , H04L43/08 , H04L43/106 , H04L45/02 , H04L45/122 , H04L45/306 , H04L45/42 , H04L45/44 , H04L45/586 , H04L45/64 , H04L45/72 , H04L45/74 , H04L45/742 , H04L45/745 , H04L47/19 , H04L49/3009 , H04L49/3063 , H04L49/354 , H04L49/9068 , H04L61/2585 , H04L67/1001 , H04L67/1038 , H04L67/568 , H04L67/63 , H04L69/321 , H04L69/326 , H04L69/329 , H04L41/5077 , H04L45/22 , H04L45/28 , H04L45/38 , H04L61/103 , H04L61/2503 , H04L67/1095 , H04L2012/4629 , H04L2101/663
Abstract: Some embodiments provide a method for handling failure at one of several peer centralized components of a logical router. At a first one of the peer centralized components of the logical router, the method detects that a second one of the peer centralized components has failed. In response to the detection, the method automatically identifies a network layer address of the failed second peer. The method assumes responsibility for data traffic to the failed peer by broadcasting a message on a logical switch that connects all of the peer centralized components and a distributed component of the logical router. The message instructs recipients to associate the identified network layer address with a data link layer address of the first peer centralized component.
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公开(公告)号:US11750532B2
公开(公告)日:2023-09-05
申请号:US16934020
申请日:2020-07-21
Applicant: VMware, Inc.
Inventor: Wenyi Jiang , Boon Seong Ang , Guolin Yang , Ying Gross
CPC classification number: H04L49/3009 , H04L12/4641 , H04L45/74 , H04L49/3063 , H04L2212/00
Abstract: Example methods and systems for logical network packet handling are described. In one example, a physical network interface controller (PNIC) may receive an ingress encapsulated packet associated with a packet flow via a physical network. The ingress encapsulated packet may include an outer header and an inner packet that is destined for a virtualized computing instance. The ingress encapsulated packet may be steered towards a processing pipeline for processing to generate a processed packet. The processing pipeline may include (a) retrieving a logical network policy associated with the packet flow from a datastore on the PNIC; and (b) performing decapsulation to remove the outer header and one or more actions on the inner packet according to the logical network policy. The processed packet may be forwarded towards the virtualized computing instance via a virtual function supported by the PNIC or a physical network connected to the PNIC.
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公开(公告)号:US11750526B2
公开(公告)日:2023-09-05
申请号:US17134110
申请日:2020-12-24
Applicant: Barefoot Networks, Inc.
Inventor: Yi Li , Michael Feng , Anurag Agrawal , Jeongkeun Lee , Changhoon Kim , Remy Chang
IPC: H04L47/625 , H04L45/7453 , H04L41/142 , H04L49/00 , H04L43/0882 , H04L43/16 , H04L45/00 , H04L45/745 , H04L45/24 , H04L47/32 , H04L47/628 , H04L49/109 , H04L47/62 , H04L49/90 , H04L69/22 , H04L49/101 , H04L12/18
CPC classification number: H04L47/6255 , H04L41/142 , H04L43/0882 , H04L43/16 , H04L45/245 , H04L45/72 , H04L45/745 , H04L45/7453 , H04L47/32 , H04L47/62 , H04L47/628 , H04L49/109 , H04L49/3063 , H04L49/90 , H04L69/22 , H04L12/1886 , H04L49/101
Abstract: Some embodiments provide a method for an ingress packet processing pipeline of a network forwarding integrated circuit (IC). The ingress packet processing pipeline is for receiving packets from a port of the network forwarding IC and processing the packets to assign different packets to different queues of a traffic management unit of the network forwarding IC. The method receives state data from the traffic management unit. The method stores the state data in a stateful table. The method assigns a particular packet to a particular queue based on the state data received from the traffic management unit and stored in the stateful table.
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