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公开(公告)号：US20050282503A1
公开(公告)日：2005-12-22
申请号：US10872947
申请日：2004-06-21
申请人： Peter Onno , Rajanish , Nitin Jain , Christopher Weigand
发明人： Peter Onno , Rajanish , Nitin Jain , Christopher Weigand
CPC分类号： H03H7/1758 , H03H7/0115 , H03H7/0123 , H03H7/1766 , H03H7/1783 , H03H7/1791 , H03H7/38 , H03H2001/0064 , H03H2001/0078
摘要： A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit's stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.
摘要翻译： 一种组合匹配和谐波抑制电路，其具有由电路的一个或多个电容或电感元件的分裂谐振提供的增加的谐波抑制电路。 在基频处，电路包括具有电容分流臂的感应串联臂。 分流臂的电容可以由两个或更多个并联路径提供，每个并联路径具有串联的电容器和电感器，使得除了提供在基频处的阻抗匹配所必需的有效电容之外，由 并行路径的串联谐振被拒绝。 以这种方式，可以使用在基频实现阻抗匹配所需的相同数量的并联元件来实现电路的阻带中的额外零点。
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公开(公告)号：US07957706B2
公开(公告)日：2011-06-07
申请号：US12701837
申请日：2010-02-08
申请人： Peter Onno , Rajanish , Nitin Jain , Christopher D. Weigand
发明人： Peter Onno , Rajanish , Nitin Jain , Christopher D. Weigand
CPC分类号： H03H7/1758 , H03H7/0115 , H03H7/0123 , H03H7/1766 , H03H7/1783 , H03H7/1791 , H03H7/38 , H03H2001/0064 , H03H2001/0078
摘要： A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit's stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.
摘要翻译： 一种组合匹配和谐波抑制电路，其具有由电路的一个或多个电容或电感元件的分裂谐振提供的增加的谐波抑制电路。 在基频处，电路包括具有电容分流臂的感应串联臂。 分流臂的电容可以由两个或更多个并联路径提供，每个并联路径具有串联的电容器和电感器，使得除了提供在基频处的阻抗匹配所必需的有效电容之外，由 并行路径的串联谐振被拒绝。 以这种方式，可以使用在基频实现阻抗匹配所需的相同数量的并联元件来实现电路的阻带中的额外零点。
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公开(公告)号：US20100201456A1
公开(公告)日：2010-08-12
申请号：US12701837
申请日：2010-02-08
申请人： Peter Onno , Rajanish , Nitin Jain , Christopher D. Weigand
发明人： Peter Onno , Rajanish , Nitin Jain , Christopher D. Weigand
IPC分类号： H03H7/38
CPC分类号： H03H7/1758 , H03H7/0115 , H03H7/0123 , H03H7/1766 , H03H7/1783 , H03H7/1791 , H03H7/38 , H03H2001/0064 , H03H2001/0078
摘要： A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit's stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.
摘要翻译： 一种组合匹配和谐波抑制电路，其具有由电路的一个或多个电容或电感元件的分裂谐振提供的增加的谐波抑制电路。 在基频处，电路包括具有电容分流臂的感应串联臂。 分流臂的电容可以由两个或更多个并联路径提供，每个并联路径具有串联的电容器和电感器，使得除了提供在基频处的阻抗匹配所需的有效电容之外，由 并行路径的串联谐振被拒绝。 以这种方式，可以使用在基频实现阻抗匹配所需的相同数量的并联元件来实现电路的阻带中的额外零点。
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公开(公告)号：US07660562B2
公开(公告)日：2010-02-09
申请号：US10872947
申请日：2004-06-21
申请人： Peter Onno , Rajanish , Nitin Jain , Christopher Dirk Weigand
发明人： Peter Onno , Rajanish , Nitin Jain , Christopher Dirk Weigand
CPC分类号： H03H7/1758 , H03H7/0115 , H03H7/0123 , H03H7/1766 , H03H7/1783 , H03H7/1791 , H03H7/38 , H03H2001/0064 , H03H2001/0078
摘要： A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit's stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.
摘要翻译： 一种组合匹配和谐波抑制电路，其具有由电路的一个或多个电容或电感元件的分裂谐振提供的增加的谐波抑制电路。 在基频处，电路包括具有电容分流臂的感应串联臂。 分流臂的电容可以由两个或更多个并联路径提供，每个并行路径具有串联的电容器和电感器，使得除了提供在基频处的阻抗匹配所需的有效电容之外，由 并行路径的串联谐振被拒绝。 以这种方式，可以使用在基频实现阻抗匹配所需的相同数量的并联元件来实现电路的阻带中的额外零点。
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5.发明授权公开(公告)号：US07392021B2
公开(公告)日：2008-06-24
申请号：US11196371
申请日：2005-08-03
申请人： Nitin Jain , Rajanish , Angelos Alexanian
发明人： Nitin Jain , Rajanish , Angelos Alexanian
CPC分类号： H03F3/189 , H03G3/3042 , H04B2001/0416
摘要： Apparatus, system, and method including a circuit including an element having an electrical impedance, an input node to receive a signal, and an output node to couple to a load; a sensing circuit coupled to the input node and the output node to sense a differential voltage between the input and output nodes and to sense a detected voltage at the input node; and a multiplier circuit to receive the differential voltage and to receive the detected voltage. The multiplier circuit provides an output voltage proportional to the instantaneous power delivered to the load based on the differential voltage, the detected voltage, and the impedance of the element. A system may further include a radio frequency (RF) power amplifier (PA). A method may further include controlling a gain of the RF PA to maintain the power delivered to the load at a predetermined level based on the output voltage of the multiplier circuit.
摘要翻译： 装置，系统和方法包括包括具有电阻抗的元件的电路，用于接收信号的输入节点和耦合到负载的输出节点; 感测电路，其耦合到所述输入节点和所述输出节点，以感测所述输入和输出节点之间的差分电压并且感测所述输入节点处的检测到的电压; 以及用于接收差分电压并接收检测到的电压的乘法器电路。 乘法器电路提供与基于差分电压，检测电压和元件的阻抗而传递给负载的瞬时功率成比例的输出电压。 系统还可以包括射频（RF）功率放大器（PA）。 方法还可以包括控制RF PA的增益，以基于乘法器电路的输出电压将输送到负载的功率保持在预定电平。
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6.发明申请公开(公告)号：US20070032209A1
公开(公告)日：2007-02-08
申请号：US11196371
申请日：2005-08-03
申请人： Nitin Jain , Rajanish , Angelos Alexanian
发明人： Nitin Jain , Rajanish , Angelos Alexanian
CPC分类号： H03F3/189 , H03G3/3042 , H04B2001/0416
摘要： Apparatus, system, and method including a circuit including an element having an electrical impedance, an input node to receive a signal, and an output node to couple to a load; a sensing circuit coupled to the input node and the output node to sense a differential voltage between the input and output nodes and to sense a detected voltage at the input node; and a multiplier circuit to receive the differential voltage and to receive the detected voltage. The multiplier circuit provides an output voltage proportional to the instantaneous power delivered to the load based on the differential voltage, the detected voltage, and the impedance of the element. A system may further include a radio frequency (RF) power amplifier (PA). A method may further include controlling a gain of the RF PA to maintain the power delivered to the load at a predetermined level based on the output voltage of the multiplier circuit.
摘要翻译： 装置，系统和方法包括包括具有电阻抗的元件的电路，用于接收信号的输入节点和耦合到负载的输出节点; 感测电路，其耦合到所述输入节点和所述输出节点，以感测所述输入和输出节点之间的差分电压并且感测所述输入节点处的检测到的电压; 以及用于接收差分电压并接收检测到的电压的乘法器电路。 乘法器电路提供与基于差分电压，检测电压和元件的阻抗而传递给负载的瞬时功率成比例的输出电压。 系统还可以包括射频（RF）功率放大器（PA）。 方法还可以包括控制RF PA的增益，以基于乘法器电路的输出电压将输送到负载的功率保持在预定电平。
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