公开(公告)号：US4733219A

公开(公告)日：1988-03-22

申请号：US19443

申请日：1987-02-26

申请人： Peter P. F. Reusens ,  Jozef D. G. L. Cannaerts

发明人： Peter P. F. Reusens ,  Jozef D. G. L. Cannaerts

IPC分类号： H03M1/00 ,  H03M1/12 ,  H03M7/00 ,  H04B14/06 ,  H04Q11/04 ,  H03M7/32

CPC分类号： H04Q11/04 ,  H03M7/304 ,  H04B14/062 ,  H03M7/3028

摘要： A prior art digital Delta-Sigma converter is improved by including a second control loop with a second forward branch coupled between the first and second subtractor circuits and a third subtractor circuit coupled in series to the first integrator circuit and with a second feedback branch and a third subtractor circuit coupled to the output of said first integrator circuit. When the input signal is equal to zero the output signal of the first integrator circuit will rapidly change to zero because the second control loop applies an additional feedback signal to the third subtractor circuit and therefore also to the first integrator circuit. Because the output signal of the first integrator output circuit signal thus more rapidly varies to zero the same is true for the output signal of the second integrator circuit and therefore also for the converter output signal.

摘要翻译： 通过包括耦合在第一和第二减法器电路之间的第二前向分支的第二控制回路和与第一积分器电路串联耦合的第三减法器电路以及第二反馈支路和 耦合到所述第一积分器电路的输出的第三减法器电路。 当输入信号等于零时，第一积分器电路的输出信号将迅速变为零，因为第二控制环路向第三减法器电路施加附加的反馈信号，因此也向第一积分器电路施加。 因为第一积分器输出电路信号的输出信号因此更快地变化到零，所以对于第二积分器电路的输出信号也是如此，因此也用于转换器输出信号。