DIGITAL CIRCUIT TESTABLE THROUGH TWO PINS
    1.
    发明申请
    DIGITAL CIRCUIT TESTABLE THROUGH TWO PINS 有权
    数字电路通过两个引脚测试

    公开(公告)号:US20120161802A1

    公开(公告)日:2012-06-28

    申请号:US13338053

    申请日:2011-12-27

    IPC分类号: G01R31/00

    CPC分类号: G01R31/318572

    摘要: A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin.

    摘要翻译: 用于集成电路的扫描测试的方法包括电路本身执行的以下步骤:在电路接通电源时,观察施加到使用引脚的位序列,其被配置为以外部速率从外部接收串行数据 时钟信号施加到时钟引脚; 当比特序列被识别为测试初始化​​序列时,以测试模式配置电路; 在移位寄存器配置中连接电路的锁存器,并且连接用于从使用引脚串联接收测试矢量的移位寄存器; 将使用引脚的传输方向切换到输出模式,以便以时钟信号的速率提供给外部串行数据; 并将移位寄存器连接到使用引脚上,作为测试结果集合提供其内容。

    Digital circuit testable through two pins
    2.
    发明授权
    Digital circuit testable through two pins 有权
    数字电路通过两个引脚进行测试

    公开(公告)号:US08928340B2

    公开(公告)日:2015-01-06

    申请号:US13338053

    申请日:2011-12-27

    IPC分类号: G01R31/26 G01R31/3185

    CPC分类号: G01R31/318572

    摘要: A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin.

    摘要翻译: 用于集成电路的扫描测试的方法包括电路本身执行的以下步骤:在电路接通电源时,观察施加到使用引脚的位序列,其被配置为以外部速率从外部接收串行数据 时钟信号施加到时钟引脚; 当比特序列被识别为测试初始化​​序列时,以测试模式配置电路; 在移位寄存器配置中连接电路的锁存器,并且连接用于从使用引脚串联接收测试矢量的移位寄存器; 将使用引脚的传输方向切换到输出模式,以便以时钟信号的速率提供给外部串行数据; 并将移位寄存器连接到使用引脚上,作为测试结果集合提供其内容。