公开(公告)号：US10559374B2

公开(公告)日：2020-02-11

申请号：US15436880

申请日：2017-02-20

申请人： Piecemakers Technology, Inc.

发明人： Gyh-Bin Wang ,  Chun-Kai Wang

IPC分类号： G11C29/12 ,  G11C29/36 ,  G11C29/48 ,  G11C29/54

摘要： A memory chip architecture includes a plurality of test pads, a plurality of interface pads, a function block and an embedded test block. The function block is coupled to the interface pads. The embedded test block is coupled to the test pads. The embedded test block is connected to an access port physical layer (PHY) through the interface pads. The interface pads are disposed between the function block and the embedded test block. The embedded test block is arranged for generating at least one test pattern as a test signal, and outputting the test signal to the function block through the interface pads to test the function block.

公开(公告)号：US20180240531A1

公开(公告)日：2018-08-23

申请号：US15436880

申请日：2017-02-20

申请人： Piecemakers Technology, Inc.

发明人： Gyh-Bin Wang ,  Chun-Kai Wang

IPC分类号： G11C29/12 ,  G11C29/36

CPC分类号： G11C29/1201 ,  G11C29/36 ,  G11C29/48 ,  G11C2029/3602

摘要： A memory chip architecture includes a plurality of test pads, a plurality of interface pads, a function block and an embedded test block. The function block is coupled to the interface pads. The embedded test block is coupled to the test pads. The embedded test block is connected to an access port physical layer (PHY) through the interface pads. The interface pads are disposed between the function block and the embedded test block. The embedded test block is arranged for generating at least one test pattern as a test signal, and outputting the test signal to the function block through the interface pads to test the function block.