Method for preventing tungsten contact/via plug loss after a backside pressure fault
    1.
    发明授权
    Method for preventing tungsten contact/via plug loss after a backside pressure fault 有权
    背面压力故障后防止钨接触/堵头损失的方法

    公开(公告)号:US06245654B1

    公开(公告)日:2001-06-12

    申请号:US09283063

    申请日:1999-03-31

    CPC classification number: H01L21/76862 H01L21/76843 H01L21/76877

    Abstract: A method for preventing tungsten contact/via plug loss after a backside pressure fault defect in a deposition chamber is provided. In the method, first deposited by a silane soak step and a tungsten nucleation layer is subsequently deposited, a plasma treating step by a H2 plasma is carried out at a temperature of not higher than 480° C. for a time period of at least 15 seconds. The plasma treating step significantly improves the uniform distribution of the silicon prenucleation layer and substantially prevents the formation of any tungsten silicide layers such that during an etchback process, the dry etchant utilized does not remove a tungsten silicide layer at a much faster rate and leads to a plug loss defect.

    Abstract translation: 提供了一种用于在沉积室中的背面压力故障缺陷之后防止钨接触/经由插塞损失的方法。 在该方法中,首先通过硅烷浸渍步骤和钨成核层沉积,通过H 2等离子体的等离子体处理步骤在不高于480℃的温度下进行至少15 秒。 等离子体处理步骤显着地改善了硅预核层的均匀分布,并且基本上防止了任何硅化钨层的形成,使得在回蚀工艺期间,所用的干蚀刻剂不会以更快的速率除去硅化钨层,并导致 插头损失缺陷。

    Method for preventing tungsten contact plug loss after a backside pressure fault
    2.
    发明授权
    Method for preventing tungsten contact plug loss after a backside pressure fault 有权
    背面压力故障后防止钨触头堵塞的方法

    公开(公告)号:US06174795B1

    公开(公告)日:2001-01-16

    申请号:US09282993

    申请日:1999-03-31

    Abstract: A method for preventing tungsten contact plug loss problem after a backside pressure fault problem in a deposition chamber is provided. In the method, first deposited by a silane soak step and a tungsten nucleation layer is subsequently deposited, a heat treating step by a rapid thermal process is carried out at a temperature of at least 600° C. for a time period of at least 10 seconds. The heat treating step significantly improves the uniform distribution of the silicon prenucleation layer and substantially prevents the formation of any tungsten silicide layers such that during an etchback process, the dry etchant utilized does not remove a tungsten silicide layer at a much faster rate and thereby does not result in a plug loss problem.

    Abstract translation: 提供了一种用于在沉积室中的背面压力故障问题之后防止钨接触塞损耗问题的方法。 在该方法中,首先通过硅烷浸渍步骤和钨成核层沉积,通过快速热处理的热处理步骤在至少600℃的温度下进行至少10 秒。 热处理步骤显着地改善了硅预核层的均匀分布,并且基本上防止了任何硅化钨层的形成,使得在回蚀工艺期间,所用的干蚀刻剂不会以更快的速度除去硅化钨层,从而 不会导致插头丢失问题。

    Portable electrical device
    3.
    发明授权
    Portable electrical device 有权
    便携式电气设备

    公开(公告)号:US08849341B2

    公开(公告)日:2014-09-30

    申请号:US13593946

    申请日:2012-08-24

    CPC classification number: G06F1/1698 H01Q1/2266 H01Q1/48 H01Q1/52

    Abstract: A portable electrical device including an antenna radiation body, a wireless communication module and a cable is provided. The antenna radiation body transceives a first radio frequency (RF) signal belonging to a first frequency band. The wireless communication module processes the first RF signal. The cable connects the antenna radiation body with the wireless communication module to transmit the first RF signal. The cable has multiple grounding points. The distances between the neighboring grounding points are less than a quarter wavelength of a signal corresponding to the first frequency band.

    Abstract translation: 提供了包括天线辐射体,无线通信模块和电缆的便携式电气设备。 天线辐射体收集属于第一频带的第一射频(RF)信号。 无线通信模块处理第一RF信号。 电缆将天线辐射体与无线通信模块连接,以传输第一RF信号。 电缆有多个接地点。 相邻接地点之间的距离小于对应于第一频带的信号的四分之一波长。

    Method of forming improved rounded corners in STI features

    公开(公告)号:US07148120B2

    公开(公告)日:2006-12-12

    申请号:US10948934

    申请日:2004-09-23

    CPC classification number: H01L21/76235 H01L21/76232

    Abstract: A method for forming a shallow trench isolation (STI) structure with improved electrical isolation performance including providing a semiconductor substrate including an overlying silicon oxide layer on the semiconductor substrate and a hardmask layer on the silicon oxide layer; dry etching in a first etching process to form a patterned hardmask opening for etching an STI opening; dry etching in a second etching process the semiconductor substrate to form an upper portion of an STI opening to form a polymer layer along sidewall portions of the STI opening; and, dry etching in a third etching process the STI opening to form rounded bottom corners and rounded top corners.

    DISPOSABLE CUP WITH STRAW
    5.
    发明申请

    公开(公告)号:US20200024024A1

    公开(公告)日:2020-01-23

    申请号:US16039375

    申请日:2018-07-19

    Applicant: Po-Jen Chen

    Inventor: Po-Jen Chen

    Abstract: The disposable cup includes a cup body and a straw. The cup body has a tube and a bottom connected to an end of the tube. The straw is directly connected to the tube at an outside position adjacent to the bottom, and communicating with the tube.

    Method of forming improved rounded corners in STI features
    6.
    发明申请
    Method of forming improved rounded corners in STI features 有权
    在STI特征中形成改进的圆角的方法

    公开(公告)号:US20060063348A1

    公开(公告)日:2006-03-23

    申请号:US10948934

    申请日:2004-09-23

    CPC classification number: H01L21/76235 H01L21/76232

    Abstract: A method for forming a shallow trench isolation (STI) structure with improved electrical isolation performance including providing a semiconductor substrate including an overlying silicon oxide layer on the semiconductor substrate and a hardmask layer on the silicon oxide layer; dry etching in a first etching process to form a patterned hardmask opening for etching an STI opening; dry etching in a second etching process the semiconductor substrate to form an upper portion of an STI opening to form a polymer layer along sidewall portions of the STI opening; and, dry etching in a third etching process the STI opening to form rounded bottom corners and rounded top corners.

    Abstract translation: 一种用于形成具有改善的电绝缘性能的浅沟槽隔离(STI)结构的方法,包括提供包括半导体衬底上的上覆硅氧化物层的半导体衬底和氧化硅层上的硬掩模层; 在第一蚀刻工艺中进行干蚀刻以形成蚀刻STI开口的图案化硬掩模开口; 在第二蚀刻工艺中干法蚀刻半导体衬底以形成STI开口的上部,以沿STI开口的侧壁部分形成聚合物层; 并且在第三蚀刻工艺中进行干蚀刻,STI打开以形成圆角的底角和圆角顶角。

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