公开(公告)号：US20210020778A1

公开(公告)日：2021-01-21

申请号：US16663365

申请日：2019-10-25

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Hung-I Su ,  Chang-Chin Ho ,  Yong-Kang Jiang

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/66

摘要： A shield gate MOSFET includes an epitaxial layer having a first conductivity type, a plurality of trenches in the epitaxial layer, a shield gate disposed in the trenches, a control gate on the shield gate in the trenches, an insulating layer between the shield gate and the epitaxial layer, a gate oxide layer between the control gate and the epitaxial layer, an inter-gate oxide layer between the shield gate and the control gate, a first doped region in the epitaxial layer at the bottom of the trenches, and a second doped region between the bottom of the trenches and the first doped region. The first doped region has a second conductivity type, and the second doped region has the first conductivity type, and thus the leakage path may be reduced in the presence of the second doped region so as to improve breakdown voltage.

公开(公告)号：US11916141B2

公开(公告)日：2024-02-27

申请号：US17505662

申请日：2021-10-20

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Hung-I Su ,  Chang-Chin Ho ,  Yong-Kang Jiang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/407 ,  H01L29/66734

摘要： A method for fabricating a shield gate MOSFET includes forming an epitaxial layer having a first conductivity type, forming a plurality of trenches in the epitaxial layer, forming a first and a second doped regions in the epitaxial layer at a bottom of each of the trenches, wherein the first doped region has a second conductivity type, and the second doped region has the first conductivity type. An insulating layer and a conductive layer as a shield gate are orderly formed in each of the trenches, and a portion of the conductive layer and the insulating layer are removed to expose a portion of the epitaxial layer in the trenches. An inter-gate oxide layer and a gate oxide layer are formed in the trenches, and a control gate is formed on the inter-gate oxide layer in the plurality of trenches.

公开(公告)号：US20230144304A1

公开(公告)日：2023-05-11

申请号：US17674843

申请日：2022-02-18

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Chien-Le Chang ,  Chang-Chin Ho ,  Yong-Kang Jiang

IPC分类号： H01L29/423 ,  H01L29/417

CPC分类号： H01L29/4236 ,  H01L29/41775

摘要： The present disclosure provides a semiconductor structure including a substrate, a first gate structure, and a second gate structure. The substrate includes at least one first trench group and at least one second trench group spaced apart from each other. The first trench group includes first trenches spaced apart from each other in a first direction and extending in a second direction other than the first direction. The second trench group includes second trenches spaced apart from each other in the second direction and extending in the first direction. The first gate structure is disposed in each of the first trenches and extends in the second direction. The second gate structure is disposed in each of the second trenches and extends in the first direction.