公开(公告)号：US11610621B1

公开(公告)日：2023-03-21

申请号：US17486871

申请日：2021-09-27

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shou-Zen Chang ,  Ming-Han Liao ,  Min-Cheng Chen ,  Hiroshi Yoshida

IPC分类号： G11C11/22 ,  H01L27/11507

摘要： An oxide semiconductor based FRAM is provided in the present invention, including a substrate, a write electrode on the substrate, a ferroelectric dielectric layer on the write electrode, an oxide semiconductor layer on the ferroelectric dielectric layer, a source and a drain respectively on the oxide semiconductor layer and spaced apart at a distance, wherein the source and the drain are further connected to a plate line and a bit line respectively, a gate insulating layer on the source, the drain and the oxide semiconductor layer, and a word line on the gate insulating layer, wherein the word line, the oxide semiconductor layer, the ferroelectric dielectric layer and the write electrode overlapping each other in a direction vertical to the substrate.

公开(公告)号：US20230079629A1

公开(公告)日：2023-03-16

申请号：US17991788

申请日：2022-11-21

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Ping Lee ,  Wen-Hsien Chen

IPC分类号： H01L27/146

摘要： The present disclosure provides an image sensing module including a main board and an image sensor. The main board has a first surface and a second surface opposite to each other. The image sensor is disposed on the first surface of the main board and includes a plurality of isolation structures and a photoelectric conversion element between the plurality of isolation structures. A first angle is provided between a light incident surface of the photoelectric conversion element and the first surface of the main board, and a second angle is provided between a light beam incident to the light incident surface of the photoelectric conversion element and a normal vector of the light incident surface. The second angle is about equal to the Brewster angle at the interface of the light beam incident to the light incident surface.

公开(公告)号：US20230038759A1

公开(公告)日：2023-02-09

申请号：US17403871

申请日：2021-08-16

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shou-Zen Chang ,  Ming-Han Liao ,  Min-Cheng Chen ,  Hiroshi Yoshida

IPC分类号： H01L27/11507

摘要： A ferroelectric memory structure including a first conductive line, a second conductive line, and a memory cell is provided. The second conductive line is disposed on the first conductive line. The memory cell is disposed between the first and second conductive lines. The memory cell includes a switch device and a ferroelectric capacitor structure. The switch device is disposed between the first and second conductive lines. The ferroelectric capacitor structure is disposed between the first conductive line and the switch device. The ferroelectric capacitor structure includes ferroelectric capacitors electrically connected. Each of the ferroelectric capacitors includes a first conductive layer, a second conductive layer, and a ferroelectric material layer. The second conductive layer is disposed on the first conductive layer. The ferroelectric material layer is disposed between the first conductive layer and the second conductive layer. The ferroelectric material layers in the ferroelectric capacitors have different top-view areas.

公开(公告)号：US20230018214A1

公开(公告)日：2023-01-19

申请号：US17398017

申请日：2021-08-10

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Chun-Lin Lu ,  Shou-Zen Chang ,  Ying-Tsung Chu ,  Chi-Ming Chen

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18

摘要： The invention provides a semiconductor bonding structure, the semiconductor bonding structure includes a first chip and a second chip which are bonded with each other, the first chip has a first bonding pad and the second bonding pad contacted and electrically connected to each other on a bonding interface, the first bonding pad and the second bonding pad are made of copper, and a heterogeneous contact combination in the first chip, the heterogeneous contact combination comprises a contact stack structure of a copper element, a tungsten element and an aluminum element, the tungsten element is located between the copper element and the aluminum element

公开(公告)号：US11552093B2

公开(公告)日：2023-01-10

申请号：US16952078

申请日：2020-11-19

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Zih-Song Wang

IPC分类号： H01L27/1157 ,  H01L27/11582 ,  H01L29/78

摘要： A 3D NAND flash memory device includes a substrate, a source line on the substrate, a stacked structure on the source line, a bit line on the stacked structure, and a columnar channel portion. The stacked structure includes a first select transistor, memory cells, and a second select transistor, wherein the first select transistor includes a first select gate, the memory cells include control gates, and the second select transistor includes a second select gate. The columnar channel portion is extended axially from the source line and penetrates the stacked structure to be coupled to the bit line. The first select transistor includes a modified Schottky barrier (MSB) transistor to generate direct tunneling of majority carriers to the columnar channel portion to perform a program operation or an erase operation.

公开(公告)号：US20220399436A1

公开(公告)日：2022-12-15

申请号：US17892665

申请日：2022-08-22

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： WEI-YU LIN ,  CHUAN-CHIEH LIN ,  SHIH-HAO CHENG

IPC分类号： H01L49/02 ,  H01L23/00 ,  H05K1/02 ,  H01G2/06

摘要： A capacitor is made using a wafer, and includes structural elevation portions to allow an electrode layer in the capacitor to be extended along surface profiles of the structural elevation portions to thereby increase its extension length, so as to reduce capacitor area, simplify capacitor manufacturing process and reduce manufacturing cost.

公开(公告)号：US11496119B1

公开(公告)日：2022-11-08

申请号：US17396771

申请日：2021-08-09

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Tomofumi Kitani

IPC分类号： H03K3/037 ,  H03F3/45 ,  H03K19/20 ,  H03K3/017

摘要： An oscillator circuit is provided. A first and a second cycle generating units, and a first and a second duty generating units are included. An SR latch, receiving outputs the first and second cycle generating units. In the SR latch, an output is provided to the first cycle generating unit and the third duty generating, and a contemporary output is provided to the second cycle generating unit and the second duty generating unit. A logic circuit receives the outputs of the first and the second duty generating units and the output and the contemporary output of the SR latch to generate a clock signal. The first and the second cycle generating units are respectively operated to provide the even and odd cycle times of the clock signal. The first and the second duty generating units are respectively operated to provide the even and odd duties of the clock signal.

公开(公告)号：US11417650B2

公开(公告)日：2022-08-16

申请号：US16925308

申请日：2020-07-09

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Chieh Pu ,  Jih-Wen Chou ,  Chih-Chung Tai

IPC分类号： H01L27/088 ,  H01L21/8234

摘要： An integrated circuit including a substrate, a first semiconductor element, and a second semiconductor element is provided. The substrate has a high voltage region and a low voltage region separated from each other. The first semiconductor element is located in the high voltage region. The first semiconductor element includes a first oxide layer and a first gate. The first oxide layer is embedded in the substrate. The first gate is located on the first oxide layer. The first gate is a polycrystalline gate. The second semiconductor element is located in the low voltage region. The second semiconductor element includes a second oxide layer and a second gate. The second oxide layer is embedded in the substrate. The second gate is located on the second oxide layer. The second gate is a metal gate. A manufacturing method of an integrated circuit is also provided.

公开(公告)号：US11367728B2

公开(公告)日：2022-06-21

申请号：US17075708

申请日：2020-10-21

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Ping Lee ,  Shyng-Yeuan Che ,  Hsiao-Pei Lin ,  Po-Yi Wu ,  Kuo-Fang Huang

IPC分类号： H01L27/108 ,  H01L49/02

摘要： Provided is a memory structure including first and second transistors, an isolation structure, a conductive layer, and a capacitor. The first transistor and the second transistor are disposed on a substrate. Each of the first and second transistors includes a gate disposed on the substrate and two source/drain regions disposed in the substrate. The isolation structure is disposed in the substrate between the first and the second transistors. The conductive layer is disposed above the first transistor and the second transistor, and includes a circuit portion, a first dummy portion, and a second dummy portion, wherein the circuit portion is electrically connected to the first transistor and the second transistor, the first dummy portion is located above the first transistor, and the second dummy portion is located above the second transistor. The capacitor is disposed on the substrate and located between the first dummy portion and the second dummy portion.

公开(公告)号：US11362099B2

公开(公告)日：2022-06-14

申请号：US16869593

申请日：2020-05-08

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Ching-Hua Chen ,  Bing-Chen Ji ,  Shun-Tsung Yu ,  Ming-Yuan Lin ,  Han-Chao Lai ,  Jih-Wen Chou ,  Chen-Chiu Hsue

IPC分类号： H01L27/11521 ,  H01L27/112

摘要： A non-volatile memory device includes a substrate, a stacked structure, an anti-fuse gate, a gate dielectric layer, a first doping region, and a second doping region. The stacked structure is formed on the substrate and includes a floating gate, a select logic gate, a logic gate dielectric layer, and an inter-polysilicon layer dielectric layer. The select logic gate is disposed on the floating gate, the logic gate dielectric layer is disposed between the floating gate and the substrate, and the inter-polysilicon layer dielectric layer is disposed between the floating gate and the select logic gate. The anti-fuse gate is disposed on the substrate, and the gate dielectric layer is disposed between the anti-fuse gate and the substrate. The first doping region is formed in the substrate at one side of the floating gate. The second doping region is formed in the substrate between the floating gate and the anti-fuse gate.