公开(公告)号：US20040023484A1

公开(公告)日：2004-02-05

申请号：US10292589

申请日：2002-11-13

Applicant: ProMOS Technologies, Inc.

Inventor： Chun-Che Chen ,  Tza-Hao Wang

IPC: H01L021/38

CPC classification number: H01L21/76808

Abstract: A method for manufacturing a semiconductor device includes providing a dielectric layer over a substrate, providing a first photoresist layer over the dielectric layer, patterning and defining the first photoresist layer, etching the first photoresist layer and the dielectric layer to form a plurality of vertical openings, removing the first photoresist layer, depositing a second photoresist layer over the dielectric layer, wherein the second photoresist layer fills the plurality of vertical openings, removing only a portion of the second photoresist layer deposited over the dielectric layer, wherein the second photoresist layer has a first substantially uniform thickness over the dielectric layer, depositing an anti-reflection coating layer over the second photoresist layer, providing a third photoresist layer over the anti-reflection coating layer, patterning and defining the third photoresist layer, and etching the anti-reflection coating layer and the second photoresist layer to form a plurality of trenches in the dielectric layer.

Abstract translation: 一种制造半导体器件的方法包括在衬底上提供介电层，在电介质层上提供第一光致抗蚀剂层，图案化和限定第一光致抗蚀剂层，蚀刻第一光致抗蚀剂层和电介质层以形成多个垂直开口 去除所述第一光致抗蚀剂层，在所述电介质层上沉积第二光致抗蚀剂层，其中所述第二光致抗蚀剂层填充所述多个垂直开口，仅去除沉积在所述电介质层上的所述第二光致抗蚀剂层的一部分，其中所述第二光致抗蚀剂层具有 在所述电介质层上的第一基本均匀的厚度，在所述第二光致抗蚀剂层上沉积抗反射涂层，在所述抗反射涂层上方提供第三光致抗蚀剂层，图案化和限定所述第三光致抗蚀剂层，以及蚀刻所述抗反射 涂层和第二光致抗蚀剂层 rm是电介质层中的多个沟槽。