公开(公告)号：US20130222029A1

公开(公告)日：2013-08-29

申请号：US13756283

申请日：2013-01-31

Applicant: QUALCOMM INCORPORATED

Inventor： Benjamin J. Bowers ,  Joshua L. Puckett

IPC: H03K3/02

CPC classification number: H03K3/02 ,  G06F9/3869 ,  H03K5/135

Abstract: A hold pulse latch is located in a data path between an output of a launch pulse latch and an input of a capture pulse latch. The hold pulse latch is configured to latch, and hold for the input of the capture patch, the output of the launch pulse latch in response to a hold pulse on its enable input. Optionally, at higher voltages, and frequency is high the launch pulse latch is changed to a transparent buffer mode. Optionally, the hold pulse latch is placed midway through the logic path between the launch pulse latch and the capture pulse latch.

Abstract translation: 保持脉冲锁存器位于发射脉冲锁存器的输出和捕获脉冲锁存器的输入之间的数据路径中。 保持脉冲锁存器被配置为响应于其使能输入上的保持脉冲来锁存并保持捕获补丁的输入，启动脉冲锁存器的输出。 可选地，在较高电压下，并且频率高，启动脉冲锁存器被改变为透明缓冲器模式。 可选地，保持脉冲锁存器位于启动脉冲锁存器和捕获脉冲锁存器之间的逻辑路径的中途。